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The design and physical implementation of a self-controlling dynamically reconfigurable system is described in detail. The reconfiguration control logic and target application execute in parallel within the same FPGA. In addition, the data required for each reconfiguration is generated on demand. A pattern-matching algorithm is used to investigate the viability of systems that exhibit self-control of reconfiguration management. The system was engineered on a custom development platform, based around a Xilinx XC6216 FPGA. The methodology and development tools used in the design are also evaluated. Initial measures of performance and recommendations for future device design are presented.

New design methods and tools are needed to improve the process of designing dynamically reconfigurable logic. This paper reports on the revision and extension of Dynamic Circuit Switching (DCS), a CAD tool for specifying and simulating dynamically reconfigurable systems. The work introduces a new design framework, which exploits existing design practices where feasible, and proposes a new design flow for reconfigurable logic.

The design of reconfigurable systems is currently an area of intense interest within the programmable logic community. One of the main obstacles to the widespread adoption of this technology is the relative immaturity of the associated design methodologies and tools. This paper reports on a development environment and associated tools for the implementation and debugging of reconfigurable applications. These tools are part of a larger program of work to improve the construction of reconfigurable systems. The current environment is specific to a custom Xilinx XC6200 development board, but the principles are generic and portable to other reconfigurable systems and architectures.

Stack filters are a class of non-linear, digital filters whose behaviour is defined by Positive Boolean Functions rather than the multiply-accumulate, arithmetic operators that are widely used in conventional digital filters. The implementation of stack filters that can be adapted in real-time is feasible using dynamically reconfigurable FPGAs. This paper reports on efforts to map adaptive stack filter architectures for image processing onto current FPGAs and to assess the potential for more efficient filter synthesis with newer device architectures.

Dynamic Circuit Switching (DCS) was the first CAD tool to allow the specification and simulation of dynamically reconfigurable logic. It was designed to be extensible to cope with new FPGA architectures. The use of DCS to simulate the operation of two new families of dynamically reconfigurable FPGAs is considered in this paper. The top-down strategy of DCS is also compared with an alternative bottom-up technique that has recently been reported.

State-of-the-art FPGAs are just capable of implementing PCI bus initiator and target functions at the original bus speed of 33 MHz. This paper reports on the use of a Xilinx 4000 series FPGA and LogiCore macros to implement a fully compliant PCI card for a specialist data acquisition application. The design required careful performance analysis and manual intervention during the design process to ensure successful operation.

Field Programmable Gate Arrays (FPGAs) and reconfigurable crossbar switches currently represent distinct classes of integrated circuits. There is a need, however, for user-programmable devices that can provide both digital logic and fast, reconfigurable crossbar switching of digital signals within a single package. An investigation into the use of dynamically reconfigurable FPGAs for this purpose demonstrated that these devices can be used for certain classes of applications requiring logic and real-time, reconfigurable switching. The study exposed a number of deficiencies of current architectures and revealed that new FPGAs, with modest architectural enhancements, could achieve better system performance.

A prototyping environment specifically designed for research into dynamically reconfigurable logic is presented. The system provides for the rapid prototyping of designs which exploit the intrinsic dynamic reconfigurability of certain types of FPGAs. The development environment is universal in that it can accommodate a range of current and future FPGA architectures with only minor modification and also provides a flexible interface to host computer platforms so that it can be used with all of the major CAD tools.