Search

Industry standard yield models make no provision for the heterogeneity of defect density or indication of how the uncertainty of defect density is propagated to uncertainty of die per wafer yield. In this paper we show how standard models can be extended by causal analysis to improve their generality. Causal diagrams are employed to specify yield models and make their assumptions transparent. Worked examples are provided as well as all the open-source code needed for the analyses.

A machine-learning model is presented that effectively partitions historical process data into outlier and inlier subpopulations. This is necessary in order to avoid using outlier data to build a model for detecting process instability. Exact control limits are given without recourse to approximations and the error characteristics of the control model are derived. A worked example for contamination control is presented along with the machine learning algorithm used and all the programming statements needed for implementation.

Engineers are continually faced with decisions about how much data they can collect. In this work, we present a statistically-based smart sampling methodology which can be used to target data collection and ensure that the risk to the product is clearly understood. Smart sampling combines knowledge of the distributions of control statistics with knowledge of the run length distributions they induce to balance the cost of information against the ability to respond to anomalies. We define and explore three characteristics that any sampling plan deemed “smart” must explicitly address: control errors that are associated with basing decisions on sample data, jeopardy that is associated with uncertainty about the true condition of the process, and the switching mechanism that controls the dynamic response to the latest information about the process. We show how the interplay of these characteristics can be exploited to comprehend the merits of a sampling plan. Practical examples of optical product inspection and process defectivity control are presented and explained.

The merits of a robust Statistical Process Control (SPC) methodology have long been established. In response to the numerous SPC rule combinations, processes, and the high cost of containment, the Instability Index (ISTAB) is presented as a tool for managing these complexities. ISTAB focuses limited resources on key issues and provides a window into the stability of manufacturing operations. ISTAB takes advantage of the statistical nature of processes by comparing the observed average run length (OARL) to the expected run length (ARL), resulting in a gap value called the ISTAB index. The ISTAB index has three characteristic behaviors that are indicative of defects in an SPC instance. Case 1: The observed average run length is excessively long relative to expectation. ISTAB > 0 is indicating the possibility that the limits are too wide. Case 2: The observed average run length is consistent with expectation. ISTAB near zero is indicating that the process is stable. Case 3: The observed average run length is inordinately short relative to expectation. ISTAB The probability distribution of run length is the basis for establishing an ARL. We demonstrate that the geometric distribution is a good approximation to run length across a wide variety of rule sets. Excessively long run lengths are associated with one kind of defect in an SPC instance; inordinately short run lengths are associated with another. A sampling distribution is introduced as a way to quantify excessively long and inordinately short observed run lengths. This paper provides detailed guidance for action limits on these run lengths. ISTAB as a statistical method of review facilitates automated instability detection. This paper proposes a management system based on ISTAB as an enhancement to more traditional SPC approaches.

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17mm2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

C045 node (65nm half pitch) technology processes are driving the development of immersion lithography techniques and infrastructures and C032 node (45nm half pitch) is following in its tracks. As semiconductor development enters the arena of low leakage, high-performance devices using immersion lithography, the 45nm hp technology adds more pressure of decreasing pitches and feature sizes using the most cost effective method available. The Crolles2 Alliance is in the first phases of the push for very low k1 193nm lithography for our technology development. Many resolution enhancement techniques are being explored to fill the low k1 realm; including implementation of these techniques and more aggressive integrations to support the device parameters. However, the early development of 45nm hp node along with the need for better focus and dose control algorithms, imaging of pitches to allow for the packing density will present significant challenges to photolithography even when considering super hyper-NA immersion lithography. Reflectivity variations, thin film interference through the complex film stacks, and increased sensitivity to feature size is posing a challenge for maintaining good and consistent features. This paper discusses an analysis and early results covering the beginning development of 45nm hp with >1NA immersion lithography. Specifically, parameters such as illumination and enhancement techniques, processing capability, application of OPC at a very low k1, process integration, mask effects, and defectivity as discussed.

The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle. In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.

Semiconductor manufacturers work hard to shrink critical dimensions in their device architectures and are in the midst of the 45nm node development. Generally, for the 65nm node, critical layers are processed using 193-nm scanners with numerical apertures up to 0.85 and non-immersion technology. It is clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) need to be examined, especially as the industry turns its attention towards the 45-nm technology generation. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. In this paper, we report on the progress of development for the 45nm device level lithography with imaging systems >1NA at the Crolles 2 Alliance. Our continued focus is the insertion of an immersion lithography process into an established pilot manufacturing line to support 45nm process development. We will present immersion resist performance, OPC feasibility, process integration, and defectivity comparisons. Finally, conclusions will be made as to the overall readiness of immersion to support 45nm node processing.

The lithography prognosticator of the early 1980's declared the end of optics for sub-0.5mm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k 1 . Several author have recently discussed manufacturing imaging solutions for sub-0.3k 1 and the integration challenges. Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k 1 imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.

The introduction of immersion lithography in the production phase has been accompanied with high level of defects compared to standard process on dry lithography. Continuous process optimization allowed us to reduce the defectivity to dry lithography level. This learning cycle also permitted to improve our knowledge on immersion defectivity formation. Immersion lithography process cause specific defects type as watermarks, bubbles, extra pattern and swelling of lines. We will report in this article on our latest experiment on the understanding of defects formation during immersion process. The influence of the track and scanner parameters has been investigated as well as materials issue (resist, topcoat). Measurements of leaching, receding contact angle and water uptake have been performed in order to correlate with defect formation. It appears that material, track and scanner parameters play different role on the formation of specific immersion defects.

The semiconductor industry will soon be putting >=1.07NA 193nm immersion lithography systems into production for the 45nm device node and in about three years will be putting >=1.30NA systems into production for the 32nm device node. For these very high NA systems, the maximum angle of light incident on a 4X reticle will reach ~16 degrees and ~20 degrees for the 45nm and 32nm nodes respectively. These angles can no longer be accurately approximated by an assumption of normal incidence. The optical diffraction and thin film effects of high incident angles on the wafer and on the photomask have been studied by many different authors. Extensive previous work has also investigated the impact of high angles upon hard (e.g., F-doped silica) thick (>700μm) pellicles for 157nm lithography, e.g.,. However, the interaction of these high incident angles with traditional thin (< 1μm) organic pellicles has not been widely discussed in the literature. In this paper we analyze the impact of traditional thin organic pellicles in the imaging plane for hyper-NA immersion lithography at the 45nm and 32nm nodes. The use of existing pellicles with hyper-NA imaging is shown to have a definite negative impact upon lithographic CD control and optical proximity correction (OPC) model accuracy. This is due to the traditional method of setting organic pellicle thickness to optimize normally incident light transmission intensity. Due to thin film interference effects with hyper-NA angles, this traditional pellicle optimization method will induce a loss of high spatial frequency (i.e., high transmitted angle) intensity which is similar in negative impact to a strong lens apodization effect. Therefore, using simulation we investigate different pellicle manufacturing options (e.g., multi-layer pellicle films) and OPC modeling options to reduce the high spatial frequency loss and its impact.

Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

On-going complex integration schemes and developments in processes present significant challenges to lithography in manufacturing advanced semiconductor integrated circuits. Although APC solutions are in place to assist in achieving robust CD control and overlay, there is a great need to increase the 'knowledge' of the system with respect to other contributors impacting the process. The problem becomes more complex in case of an ASIC Prototyping Fab where there is no big runner concept. This leads to the need of a product effect management requirement (Product layout and reticles impact). For this reason, we developed the multivariate R2R controller. This paper discusses the multi-variant methodology and results of a new R2R regulation algorithm in a 65nm node process. Specifically, parameters such as linear combinations of terms, alignment variation for overlay modeled parameters (inter-field / intra-field), CD impacts (reticles, process, tool, STI stack etc) are studied. New solutions for future technology nodes are presented in this paper. It includes for each contributor a multivariate method to assess vector responses and noise contribution. This is being applied on CD and Overlay measurement feedback. For each source of variation (or "Contributor"), the multivariate controller provides the estimated level of compensation requested to meet the target and the level of noise induced on lot processing. At the moment the multivariate R2R controller runs in production. A real evaluation of the existing sources of variations and noise is possible and demonstrated. The result is a significant regulation performance improvement.

The greatest challenge for 65-nm contact holes and via printing is ensuring an acceptable process window (250-nm DoF @ 8% EL) for a wide range of pitches with a MEEF lower than 3.5. To print dense contact holes / vias with a CD less than 100-nm, very high Numerical Apertures (≥ 0.85) are required. Consequently DoF through pitch is dramatically reduced, such that it becomes absolutely necessary to develop new techniques to enhance process latitude. In this paper, we will study the use of customized illuminations formed by combination of small radius conventional illumination and quasar. Generically, this type of illumination is commonly referred to as 5-pole illumination. Specifically this paper, the “windmill” and “soft quasar” options are investigated. These designs are based upon the assumption, that there is a way to optimize for all pitches, the imaging lens pupil filling with diffracted orders. Using a combination of aerial image simulations and experimental (double) exposures, the optimal 5-pole illumination designs are derived, with their simulated performance being compared to conventional illumination settings. For the optimised designs, experimental data is presented for “real” device structures based on the Crolles2 65-nm technology design rules.

In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor [1], improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented. In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.

The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.

The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (packing density) a scanner is also expected to provide tight control of the Across Chip Linewidth Variation, ACLV, (transistor speed). An important component of ACLV is lens aberrations. Techniques that measure in-situ the lens aberrations are now available. In a previous paper we reported good agreement between the first 25 Zernike coefficients measured in-situ using one of these techniques ARTEMIS and PMI (Phase Metrology Interferometry) data collected at the lens manufacturer. However questions have arisen as to the practicality of ARTEMIS, especially in view of its heavy reliance on a very large number of SEM images. We have measured the first 25 Zernike coefficients for 13 ASML 500/700 DUV Step & Scan systems in a high-volume wafer fab. In this paper we report on certain enhancements that were made to the best practice of ARTEMIS. We will also present a summary of the measurements taken and our first attempt to cluster the tools according to the aberrations measured.

In a joint development program between ASML and Motorola a new set of alignment marks have been designed and tested using the ATHENA off-axis alignment system on the ASML scanner. The new marks were analyzed for improved robustness against varying wafer-processing conditions to verify improved overlay capability and stability. These new marks have been evaluated on a set of dual inlaid-copper short flow wafers, with layer stacks consisting of 180 nm technology generation dielectric materials. Typical process variation has been deliberately introduced as part of the designed experiment to study the performance robustness of the new alignment marks. This paper discusses the new mark design and the theoretical reasons for mark design and/or integration change. Results shown in this paper provide initial feedback as to the viability of new variations of ATHENA alignment marks, specifically the SSPM and VSPM. Included in the results is the investigation to further stabilization of alignment signal strength. New ideas that are currently under development, to increase alignment mark signal strength stability, are discussed.

This paper demonstrates a method of analysis to determine a minimum achievable overlay design rule, for an existing stepper tool set in a high volume manufacturing fab. Overlay parameters and Critical Dimensions are considered in an overlay budget applying a modified algorithm to the evaluation of reticle errors, tool performance, and design rule analysis. The modified algorithm is used to determine the capability of an installed tool set of high NA steppers to meet the aggressive overlay requirements for advanced BiCMOS device performance. Design rule boundaries and tool set capability are thoroughly investigated. Experimental results from lithographic tests are used in a modified algorithm to determine the capability of running with current design rules or requiring a change for manufacturability. The impact of writing reticles to tighter specifications for both Critical Dimensions and pattern placement are considered. This study provides a method for chip designers and process engineers to determine the lithographic capability of an installed tool set where a part will eventually be fabricated. The results demonstrate that design rules demand optimum tool performance for overlay and CD control as well as provide a tool for the evaluation of continuous improvement.