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This paper will outline a novel technique for fabricating T-gates. Although dependent upon two lithographic exposures, this process is more robust and flexible than existing techniques. The resultant gates are structurally stable, with electrical resistance that can be made arbitrarily small by increasing the size of the T-gate top. Moreover, this gate process is fully compatible with existing MESFET and HEMT fabrication methods. Performance of microwave devices will be presented, contrasting 0.25 tm conventional gates with vacuum passivated T-gates. The T-gates will be shown to offer superior breakdown and gain performance and to produce FET characteristics which remain stable from gate level to final frontside.

An analysis of overlay measurements for wafers patterned by direct write lithography suggested that resist charging during electron beam exposure can produce significant pattern placement errors. This paper investigates the effect of charging for each critical level in Si processing and demonstrates how errors due to charging can be eliminated. A methodology employing Market measurements was used to provide statistically significant data on electron beam deflection. Charge accumulation in large exposed areas was found to produce offsets in the placement of registration crosses. Typical placement errors for a trilevel resist structure were 0.25 micron. Experiments showed that the magnitude of deflection was comparable for all substrate types, but increased with increasing trilevel resist thickness. These results are explained with a theoretical model which uses a Monte Carlo calculation to compute the dipole moments produced by accumulated charge. Various techniques to minimize the effect of charging were investigated. It was shown that in-creasing the electron accelerating voltage reduces beam deflection. In fact, pattern placement errors were made negligible by increasing the beam energy from 20 keV to 50 keV. In addition, both Ar ion implantation of the trilevel resist and the use of a metal trilevel structure were demonstrated to eliminate the effect of charging.

Low defect density masks are necessary to obtain the high chip yields required in VLSI technology. This paper will outline the boron nitride mask fabrication process that has been developed at AT&T Bell Laboratories, and discuss the nature and distribution of normally encountered defects. The advantages and disadvantages of various repair techniques will be addressed and specific examples of repairs made on silicon integrated circuit X-ray masks will be shown.

The diminishing size of VLSI features necessitates the use of a scanning electron microscope (SEM) for making inprocess CD measurements. The intent of this paper is to establish a methodology for improving the accuracy and precision of such measurements. In SEM metrology, the challenge lies in determining two points in the secondary electron line-scan corresponding to the feature edges. The systematic errors introduced by incorrect edge detection can be reduced greatly by optimizing the linescan with proper choice of SEM operating conditions. Experiments on two samples of interest in VLSI processing demonstrate the advantage of increased accelerating voltage for minimizing measuremental uncertainty. In addition, measuremental robustness, or sensitivity of linewidth measurement to SEM defocus, is shown to be strongly dependent upon the specific edge detection algorithm used.

Novolac reists have been widely used in microlithography due to their high resolution, thermal stability and dry etch resistance. One such resist, Shipley MP 2400, is used for both e-beam and deep UV lithography. In this paper, using e-beam lithography, we explore the effect of resist development parameters upon MP 2400 contrast and resolution. In particular, it is observed that resist contrast is strongly dependent on both developer dilution and developer temperature. Our experiments were performed using an immersion development system with a laser endpoint detector. This system facilitates controlled experiments since resist dissolution can be monitored directly during development. Another consideration in these experiments was to determine how resist contrast affects exposure dose latitude. Increased contrast is shown to improve the resolution of patterned features, but electrical linewidth data demonstrates a degradation of process latitude with respect to exposure dose. That is, linewidth variation due to either the proximity effect or focus variation will increase with increasing resist contrast. Lastly, a simple relationship is derived which enables one to predict immersion development time as a function of resist contrast.