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Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm 1 . Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Mask error factor (MEEF) is a commonly used metric in lithography. This parameter gives a good indication of the impact of intra-mask CD variation on the wafer. Unfortunately, MEEF is useless to anticipate the CD variation on the wafer induced by Mask Mean-To-Target variation (MMT). Currently, MMT error is compensated by adjusting the exposure dose. This paper presents the concept of MEV (MEEF Energy-latitude Variation) which is defined by the equation δCDwafer=MEV *δMMT after the dose compensation in a similar way to the MEEF concept. A simple expression for MEV will be presented which shows that the MEV factor is proportional to the variation of the product of EL*MEEF through the population. Using 65nm logic gate level, MEV experimentally shown to be non-zero, and roughly ½ times MEEF factor, which is of course non-negligible in sub 100nm regime. Based on aerial image simulation, pure optical effects are responsible for about 40% of the MEV, which gives a slight predominance of the resist part. Finally, the possibility of reducing the MEV factor by compensating for MTT variation not only by dose but also by illumination settings change is discussed. This will give the basis for an Advanced Process Control (APC) algorithm for the future generations.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.

The cost of developing and deploying optical proximity correction (OPC) technology has become a non-negligible part of the total lithography cost of ownership (CoO). In this paper, we present our efforts to reduce costs associated with OPC in the development phase for the 90nm node, and production phase for the 130nm node.

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift mask (high-T attPSM), where T > 14%, to improve process margins. The benefits of a high-t attPSM are substantial, but drawbacks like inspection difficulty, defect free blanks manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65nm node with 193nm lithography. Earlier work shows that the problems High-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75NA 193nm λ results for 6% versus 9% attPSM on gate, contact/via, and metal layers at 65nm generation target dimensions with leading edge resists. Additional information on the inspectability and reticle blank manufacture of % AttPSM will also be given to provide a cohesive analysis of the transition tradeoffs.

Conventional lithography techniques have been losing their ability to easily support continuous shrinking of feature sizes, especially when the pattern half-pitch is

Due to the challenging CD control and resolution requirements of future device generations, a large number of complex lithography enhancement techniques are likely to be used for random logic devices. This increased design, reticle, process and OPC complexity must be handled flawlessly by process engineers in order to create working circuits. Additionally, the rapidly increasing cost and cycletime of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have extended the capability of leading edge model-based OPC software to find and analyze process-limiting regions in real product designs. Specifically, we have implemented and verified software usefulness to find design-process limitations due to measured lens aberrations, as well as errors in focus, exposure or reticle CD control. We present results showing the applications and limitations of these new model-based analysis methods to discover process-design interaction errors in 90nm and 130nm patterning processes; and to propose design rule, process or OPC improvements to mitigate these errors.

The past few years have seen an explosion in the application of software techniques to improve lithographic printing. Techniques such as optical proximity correction (OPC) and phase shift masks (PSM) increase resolution and CD control by distorting the mask pattern data from the original designed pattern. These software techniques are becoming increasingly complicated and non-intuitive; and the rate of complexity increase appears to be accelerating [1]. The benefits of these techniques to improve CD control and lower cost of ownership (COO) is balanced against the effort required to implement them and the additional problems they create. One severe problem for users of immature and complex software tools and methodologies is quality control, [2] as it ultimately becomes a COO problem. Software quality can be defined very simply as the ability of an application to meet detailed customer requirements. Software quality practice can be defined as the adherence to proven methods for planning, developing, testing and maintaining software. Although software quality for lithographic resolution enhancement is extremely important, the understanding and recognition of good software development practices among lithographers is generally poor. We therefore start by reviewing the essential terms and concepts of software quality that impact lithography and COO. We then propose methods by which semiconductor process and design engineers can estimate and compare the quality of the software tools and vendors they are evaluating or using. We include examples from advanced process technology resolution enhancement work that highlight the need for high-quality software practices, and show how to avoid many problems. Note that, although several authors have worked in software application development, our analysis here is somewhat of a black box analysis. The black box is the software development organization of an RET software supplier. Our access to actual developers within these organizations is very limited. In so far as our comments with respect to the internal workings of these development organizations go, we rely on the interactions we have had with applications engineers and other technical specialists who provide our interface to the development organizations.

Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

It is well known that shrinking k1 factors and increasing MEEF are making it more difficult to print contact holes with acceptable latitude and low defectivity. Given the decreasing process latitude this implies, choosing elements of the lithography process independently is becoming less and less of an option. Instead all elements of the lithography process need to be chosen so that a production-worthy process can be rapidly developed. The large number of options available for building a process further complicates the optimization problem. In this study, simulation results are used to explore the tradeoffs between illumination options and reticle substrate choice as applied to contact hole printing. Relative defectivity levels are presented from logic test circuits for selected cases of illumination and reticle type. These selected cases show that what improves defectivity also improves the Normalized Image Log-Slope (NILS). As it has been previously shown that NILS is already an excellent image quality metric NILS improvement will be used as the basis of the work presented in this paper. Extensive simulations will be used to determine the best choice of illumination and mask type to maximize NILS and by implication minimize defect density.

The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k1 regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k1 range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k1, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

EUV lithography at 13nm wavelengths will require the use of reflective multi-layer mask substrates with a patterned absorbing top layer. As the height of the absorber is many times the wavelength of the exposure radiation, EUV masks are true topographical entities. Therefore, scalar Frauenhofer diffraction simulations are not completely valid and accurate. Rigorous solution of Maxwell's equations in the topography is necessary to accurately predict many of the lithographic effects of these masks. Additionally, the interactions of the non-vertical radiation reflectance from the multilayer stack with the absorber causes further non-intuitive lithographic results which need to be understood and optimized. To further the rigorous understanding of EUV mask effects, we have extended existing 2D and 3D rigorous simulators to model EUV lithography diffraction. These simulators, METRO and METROPOLE-3D respectively, use the waveguide method for fast and accurate computation of topographical mask structures. Modifications of these simulators enable an order of magnitude speedup in the calculation of results containing large numbers of EUV multilayers, improve mask dimension modeling accuracy and enable accurate modeling of the non-normal EUV source illumination through a range of pitch values. Rigorous illumination and multilayer defect analysis results will also be shown. Additional comparisons to recently published rigorous EUV simulations results and impressive runtime results on standard desktop workstations are presented. The results show that for EUV lithography the best focus position and the symmetry of the aerial image intensity profile with respect to best focus is affected by the pattern pitch.

Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.

Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation. Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed. Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.

Complementary phase shift mask (c:PSM) is one of the most promising resolution enhancement techniques (RET) to extend low k1 optical lithography. Nonetheless binary intensity mask (BIM) imaged with 193 nm wavelength at high numerical aperture (0.75) off-axis illumination (OAI) might still be used for nested through isolated feature sizes as small as 70 nm. We compare the feasibility of using c:PSM and BIM for 70nm generation technologies. Experimental results of high NA imaged BIM and c:PSM are presented.

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Recent years have shown a strong increase in the use of statistical lithography error analysis for process tuning and in making technology choices. Simulation has shown it can play an important role in this area by accurately predicting experimental critical dimension (CD) distributions. Earlier statistical lithography simulation work was based on the Response Surface Methodology. The response surface is built by simulating CD dependence on input lithography process variables of interest such as focus, dose, mask CD, resist thickness, etc. The process parameters are then sampled from the Gaussian distribution to generate the distribution of the resulting resist CDs. When a large number of input parameters are being considered in order to describe the important experimental variations, the computational runtime is rapidly increased due to the requirements to fully simulate an (N+1)-dimensional response surface, where N is the number of input parameters. The work we present here has improved the speed of statistical lithography simulations through the use of Monte Carlo technique. With this technique, the runtime of the simulations is independent of the number of input parameters. The technique can be used for 1D or 2D simulations. We present results benchmarked with 130 nm process data showing the usefulness, runtime improvements and accuracy of this method. We have also used Variable Threshold Resist model (VTRM) in conjunction with the Monte Carlo technique. VTRM was calibrated against experimental focus-exposure matrices at varying line width and pitch. The use of VTRM greatly improves the accuracy of the statistical results by the virtue of establishing a good fit to the experimental data, which can be quantified by the root mean squares of residuals. VTRM also significantly speeds up the computation, since it uses only aerial image calculation as opposed to full resist modeling. Simulation results produced by using VTRM closely match the experimental results through a range of pitches, mask line widths and various illumination conditions.

Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.

Attenuated Phase Shift Masks (Att-PSM) have been actively investigated and developed for conventional optical lithography to enhance the lithographic performance. In this paper, Att-PSM for Extreme Ultraviolet Lithography (EUVL) is compared to binary EUVL masks through simulation. Additionally, a new structural design for EUVL Att-PSM that is intended to enhance the image contrast during the inspection is also presented. Aerial image simulation for 50 and 35-nm wide contact holes was performed using an internally developed optical projection lithography simulator. Analysis of phase shift and attenuation for various combinations of Att-PSM layers was also done using an internally developed simulator based on optical multilayer thin film theory. The results of aerial image simulation agree with previously published results in that Att-PSM for EUVL provide steeper edge profile and higher peak intensity compared to the binary EUVL mask. These enhanced aerial images provide greater exposure latitude and 28 percent to 80 percent greater depth of focus for Att-PSM compared to binary masks for printing contacts. The simulations were also used to set initial targets for phase and reflectance control of the PSM stack for 35-nm contacts. Mean reflectance between 3 and 6 percent and phase of 180 +/- 10 degrees result in significantly larger DOF than for binary masks. The prototype structure simulated for an EUVL Att-PSM consists of an upper dielectric layer (SiON) and a lower metal layer (TaN or Cr) on top of Mo/Si multilayer mirror. With this dual layer scheme, satisfying the optical requirements is easier than with a single layer structure because accurate control of phase shift and attenuation is possible by controlling the thickness of both the upper and lower layers. Obtaining the desired phase shift and transmission using a single layer is difficult. The advantage of having a dielectric (SiON) top layer is that the thickness of dielectric layer can be optimized to enhance the image contrast at inspection wavelength (normally DUV) as well as to provide the desired phase shift at exposure wavelength (13.4-13.5nm). Another advantage of Att-PSM for EUVL is the reduced height of patterned structure on the multilayer mirror which provides a relative advantage in resolution by reducing the image blur caused by the shadowing effects of the taller absorber stack.

In this paper, we discuss a methodology for characterizing and comparing the lithographic process from the CD control point of view. In contrast to the traditional method of exposure latitude vs. depth of focus widely used in lithography, we use the statistical line width variation Cpk, and Cp as the measures of the lithographic process performance and capability. We have developed a software package called Megastat, which estimates CD variation based on experimental focus and exposure matrix (Bossung Curves) and assumed or independently measured focus and dose stochastic behavior. A similar approach was considered in. The impact of focus and dose control on across chip line width variation (ACLV) and across wafer line width variation (AWLV) was quantified with Megastat and compared to the experimentally obtained CD control for a particular 248nm lithographic process for the 130nm technology node. The statistical approach utilized in the Megastat software produced a very good match with the experimental results, which confirmed the usefulness of the statistical approach to characterizing the lithographic processes. We have additionally devised methods for decoupling and determining the actual experimental statistical variations inherent in lithographic processes. These methods allow the input 1 sigma variations for the statistical window analysis to be accurately determined. The usefulness of these methods will also be shown.

The patterning of very small contact hole features for the 130nm and 100nm device generations will be a difficult challenge for 193nm lithography. The depth of focus for small contacts is currently inadequate for a manufacturable process that includes both dense and isolated pitches. As higher NA 193nm scanners are not expected to improve focus margins considerably, other contact patterning methods are required which improve processing margins. In this work, we study the potential for contact photoresist reflow to be used with 193nm photoresists to increase process windows of small contact dimensions.

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designer's intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designer's intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

The use of low K1 lithography to extend Moore's Law has been shown to have large implications for random logic design rules. In this work we are continuing the analysis of process control and design rule implications of low K1 lithographic systems to include highly optimized illumination and reticle enhancement conditions. Recent 248nm and 193nm lithography results have shown considerable improvements in two-dimensional pattern transfer linearity from optimized off-axis illumination. Due to the public unavailability of leading-edge layout rules (because of their extremely proprietary nature), we are applying our analysis to the simple lambda based design rule system of Mead and Conway. We analyze the impact of K1 and optimization method by comparing the (normalized) area of a typical SRAM bitcell redesigned according to these lambda based rules. The area of the bitcell strongly depends upon the design rules required for each enhancement technique and K1 factor to achieve a manufacturable cell. These area comparisons allow for easy viewing of the cost of pursuing different low K1 strategies. The results of this work are mainly generated from simulation but are backed by experimental verification from recent 193nm tool and process developments.

Manufacturable process windows for the small contact dimensions of the 100 nm lithography generation are well beyond the capability of current 193 nm resist and exposure tool processes. Even with next generation very high NA (>0.7) 193 nm exposure tools, simulations indicate that these contact sizes are not obtainable with standard processing techniques. Therefore, we have investigated the feasibility of using a 193 nm resist reflow technique to obtain small contact hole sizes. We have chosen the Thin Imaging System 2000 (TIS2000) of ARCH Chemicals for investigation. This resist provides good process latitudes and excellent etch selectivity and has a much lower Tg compared to single layer 193 nm resists. This work will show the impact of resist flow on Focus-Exposure windows, proximity and proximity-uniformity, CD-uniformity over the wafer and mask error factor. Additional experimental results will highlight profiles after oxide etch as well as process windows achievable with a 6% attenuated phase shift mask.

Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We have grown neodymium doped mixed apatite crystals, (SrxBa1- x)5(PO4)3F, Sr5(P1-xVxO4)3F, and Ba5(P1-xVxO4)3F, and spectroscopically studied them as potential gain media for a laser source for atmospheric water sensing operating at 944.11 nm. We conclude that an appropriate apatite host material for a 944.11 nm laser should be a mixture of Sr5(PO4)3F with a small fraction of Ba5(PO4)3F. The precise wavelength tuning around 944.11 nm can be accomplished by varying the host composition, temperature, and threshold population inversion. In apatite crystals of mixed composition, the amplified spontaneous emission loss at 1.06 micrometers is predicted to be significantly smaller than that in the end members.

With design rules continuing to shrink down to 0.18 micrometer and beyond, various small OPC features have been used more and more by the semiconductor industry to increase the process latitude depth of focus), preserve the printing pattern fidelity on the wafer and extend the lifetime of photolithography technology. These various sub resolution OPC features directly challenge the inspection capability of the most advanced inspection systems. Die to die and die to database inspection capabilities must be characterized. A comprehensive 'HellOPC' test mask has been designed and developed for the OPC inspection evaluation. We have evaluated the OPC inspection capability of various OPC features for four technology levels that are 0.25 micrometer, 0.225 micrometer, 0.18 micrometer and 0.15 micrometer with Die to Die and Die to Database modes with this 'HellOPC' test mask. Runability (runability equals inspectability) maps for various technology levels and various OPC sizes have been presented. The results showed die to die inspection capability is much better than die to database for the advanced OPC inspection. The APA on KLA351 and the AOP215 on KLA353 have been evaluated in this work.

It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.

It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.

As 248 nm DUV lithography is pushed to the 0.18 micrometers generation with logic features 0.14 micrometers and below, process control requirements become severe. Previously acceptable exposure latitude variations due to substrate reflectivity have become unacceptable. Additionally, next generation 248 nm steppers with extremely narrow band laser illumination cause significant increase in substrate interference effects. These factors create stringent requirements for anti-reflective coating (ARC) optimization. We present result of experimental work to fine tune inorganic ARC thickness and optical properties for subtractive and inlaid feature types at the 0.18 micrometers generation. This work focuses on cost and time effective single wafer ARC optimization methods for extension to 300 nm wafer sizes. The methods include reflectometry, spectroscopic ellipsometry, generation of test wafers with large film thickness uniformity and calibrated simulation.

Lithographic patterning of small inlaid trenches is becoming increasingly important for leading edge semiconductor manufacturing. Correct patterning of these small inlaid features is made difficult by inherent difficulties in darkfield pattern imaging, large substrate reflectivity variations, large sensitivity to reticle CD variations and stringent requirements for the photoresist etch mask. Additionally, successful process optimization requires accurate knowledge of the lithographic errors affecting CD control. We present her a CD control error budget analysis for 0.18 um inlaid trench lithography using 0.6 NA 248 nm exposure tools and high resolution chemically amplified resist. Experiment and tuned simulation are used to translate tool, process and reticle variations into wafer CD variations. Results of across-field and across-wafer error analysis for different process choices are presented as are experimental verifications of their accuracy. Conclusions presented include the significant impact of stepper best- focus determination for across-field CD variation and the considerable overall CD control improvements observed with thin photoresist and strong phase shift processes.

We have extended the capability of a vector 3D lithography simulator METROPOLE-3D from a photomask simulator to become a full 3D photolithography simulator. It is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE- 3D consists of several simulation modules: photomask simulator which models the aerial image of any mask pattern (including phase-shifting masks); exposure simulator which models light intensity distribution within the photoresist and arbitrary underlying non-planar substrate structures; post-exposure baking module which models the photo-active compound diffusion, chemically amplified (CA) photoresist cross-linking and de-protection processes; and finally, 3D development module which models the photoresist development process using the level-set algorithm. This simulator has a wide range of applications in studying the pressing engineering problems encountered in state-of-the-art VLSI fabrication processes. The simulator has been applied to the layout printability/manufacturability analysis to study the dominant physical phenomena in lithography, deposition, CMP and etching processes that affect the transfer of mask patterns to the final etched structures on the wafers. Using this new 3D rigorous photolithography simulator, optical proximity effects have been studied. A reflective notching problem caused by the reflective substrate structure has been thoroughly studied, and an anti-reflective coating (ARC) solution to this notching problem has been optimized by the simulations. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.

This paper uses simulation and experiment to study near resolution limit patterning of contacts and damascene trenches using conventional i-line lithography. Special attention is paid to the requirements for substrate control. The patterning behavior is compared to DUV lithography results. We also evaluate the cost-of-process for an i-line process using substrate and optical enhancements compared to a standard 248 nm DUV process.

A traditional aerial image model has been used to demonstrate a good applicability of 13nm EUV projection lithography to printing sub-0.1mm features. To estimate the potential of a possible candidate for EUV optics--a two- mirror projection system, we investigated the issues of aerial image formation by the reflective optics with account for aberrations. We have developed a simplified method to determine the optical parameters of the ring-field system that minimize aberrations of the 3rd order and, partially, of the 5th. As a result, we have found that the uncompensated aberrations contribute to a sharply asymmetrical impulse response of the ring-field projection system, where the characteristic width of the impulse response in some directions might be two times larger than the diffraction limit.

A 3D planar pseudo-vector approach to modeling resist exposure has been implemented for optical projection lithography. The approach allows for high numeric aperture effects revealed by others in the resist latent images; comparisons made show its fine agreement with rigorous vector modeling up to NA value of 0.7. Fast Fourier transform technique has been applied to reduce mask and resist (including postbake) modeling runtime; the effects of finite accuracy approximations of the mask areas and mask periodicity have been investigated and compensated. The overall performance of the exposure model has been optimized to be 10X faster than for a similar vertical propagation model. A modified `cell' algorithm has also been used to model resist development; this resulted in more accurate resist profiles for the same latent image accuracy, providing additional runtime savings to resist profile simulations.

An improved method is presented for the optimization of plasma deposited bottom inorganic anti-reflective coatings (ARCs). These ARCs have shown the capability to improve photolithography profess margins through reduction of substrate reflectivity while meeting integration issues. However, the ability to vary plasma ARC optical properties through deposition conditions has led to increased complexity of film stack optimization. We present simple but effective enhanced modeling methods for reducing the effort required to properly tune plasma ARC optical conditions and optimize complex films tacks incorporating these materials.

We present a description of a software tool and a methodology for easily creating photoresist development rate parameters in lithography simulation. The tool optimizes parameters using the Modified Simplex Method. The methodology uses the tool to provide insight into the effects of the development rate parameters and to find usable parameters quickly. The reasonings behind the methodology are discussed as well as advantages and disadvantages. Results from three different lithography simulators are shown to agree well with experimental cross-section SEM data.

A new workstation-based rigorous 3D model for simulation of light scattering by alignment structures is introduced. The model extends a successful 2D lithography model, and has been applied to the simulation of periodic 3D alignment marks on a resist covered silicon substrate. The theory behind the new model is presented, and examples are given of the model's results and computational efficiency.

Rigorous simulation has been shown to be useful for predicting complicated effects in the optical lithography process. Rigorous simulation models are necessary for accurately predicting behavior from non planar mask and substrate structures and for non-vertical light propagation. As previously shown[l], the benefits of 2D rigorous lithography simulation are many, however, these models are inherently limited. 2D models are not general enough to model contact openings, corners, 3D defect structures or off-axis illumina tion systems. These are important issues in lithography today and require true 3D simulation to help analyze them.

Lithography is the critical process for developing smaller and more dimensionally accurate semiconductor structures more reliably. Many random defects are caused by contamination particles during the lithographic process. Several models have predicted yield loss associated with defect density and particle size. Although some have taken into account the defect growth mechanisms, a more accurate simulator is needed to provide the transformation from the contamination to the defect level. In this paper, the contamination to defect transformation is investigated using the 2D lithographic simulator, METROPOLE. A study is presented that characterizes the effects of particle size, location and composition on the formation of lithographic defects for a 2D metal line structure. Particle characterization and parameterization is carried out for a number of common conditions including different light polarizations, defocus, and nonplanarities. The simulations are checked against defect data from AMD Sunnyvale.

The creation of defect free and accurately biased phase shifting masks (PSMs) with correctly designed layouts is a difficult task. The behavior of PSMs, with their complicated structures and topographies, is highly sensitive to process parameters. Attenuating PSMs are becoming an important and popular mask technology, because of the manufacturing and layout difficulties associated with other PSM types. They are flexible (being useful for both isolated and repeating structures) and relatively simple to manufacture in comparison with other PSM methods (not requiring extra layers of glass or very small mask openings). In addition, the mask layout is not further complicated by multiple phase openings. However, attenuating PSMs are complicated vertical devices. The height of the attenuating material (usually chrome) and the anisotropically etched, phase shifting glass beneath the opening (See Fig. 1) have significant impact upon imaging performance. The light scattering from the vertical glass walls alters the transmitted light intensity and the defocus behavior. The percentage of light transmitted through the chrome also affects the final image considerably. Questions have also been raised about the repairability of defective masks. Recently, both DuPont Co. and Mitsubishi Corp. have introduced new attenuating PSMs where the absorber material creates the iv radians phase shift in the attenuated light [l][2] (See Fig. 2). For the creation of these new masks, anisotropic etching of the glass mask substrate is not necessary and thus one manufacturing process step is eliminated. The absorber itself is thin, approximately the thickness of the chrome for a binary transmission mask. Therefore, mask edge light scattering is greatly reduced. Mitsubishi has reported the ability to manufacture these masks with satisfactorily high film uniformity, low defect rate and high chemical durability. The successful repair of pinhole and pindot defects in the attenuating material has also been demonstrated[2]. In this work, we have been investigating performance for the standard chrome attenuating PSM and the new DuPont and Mitsubishi attenuating PSMs using the vector 2D photolithography simulator METROPOLE[3]. METROPOLE, which was developed at Carnegie Mellon University, uses the so-called waveguide method [4][5] to solve Maxwell's equations rigorously and model non-vertical light propagation, defocused reduction images, arbitrary material optical properties and light scattering from complex mask topographies. Aerial image profiles on the wafer of isolated lines are evaluated with respect to: the percent of light transmitted through the attenuator, mask opening size, attenuator height, mask bias and defocus behavior. In addition, the transmitted light intensity results were compared to those from the scalar PSM simulator SPLAT[6] to check the correctness of scalar models for performing accurate attenuating PSM biasing calculations. Defective and repaired attenuating PSM were also analyzed for possible performance degradations caused by the repair process. This research differs from previous scalar modeling studies of attenuated PSMs in that a vector simulator can properly include light scattering effects caused by the often substantial vertical structure of the attenuated PSM.

The creation of stable, defect free, and correctly biased phase shifting masks (PSMs) is a difficult task. The behavior of PSMs, with their complicated structures and topographies, is highly sensitive to process parameters. A method of equalizing the intensity transmission by applying a wet etchant to the reticle and etching back both shifted and unshifted openings has been proposed. The etchback is used to reduce or alter the sidewall light scattering effects, leading to intensity equalization. The proposed method has been shown to cause intensity equalization for i-line and DUV illuminated alternating PSMs. However, many questions remain about the effective use of this method.

A new vector (true two-dimensional) optical lithography modeling program, METROPOLE, is presented which incorporates arbitrary mask geometries. This rigorous model is thus ideally suited for the simulation of phase shifting masks. The efficiency of the electric field calculations, both within the mask and on the substrate structures, allows its use on accessible engineering workstations. Several simulation examples are presented, and include the new phase shifting on the substrate technique (POST).