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Access networks based on vertical cavity surface emitting laser (VCSEL) transmitters offer alternative solution in delivering different high bandwidth, cost effective services to the customer premises. Clock and reference frequency distribution is critical for applications such as Coordinated Universal Time (UTC), GPS, banking and big data science projects. Simultaneous distribution of both data and timing signals over shared infrastructure is thus desirable. In this paper, we propose and experimentally demonstrate a novel, cost-effective technique for multi-signal modulation on a single VCSEL transmitter. Two signal types, an intensity modulated 10 Gbps data signal and a polarization-based pulse per second (PPS) clock signal are directly modulated onto a single VCSEL carrier at 1310 nm. Spectral efficiency is maximized by exploiting inherent orthogonal polarization switching of the VCSEL with changing bias in transmission of the PPS signal. A 10 Gbps VCSEL transmission with PPS over 11 km of G.652 fibre introduced a transmission penalty of 0.52 dB. The contribution of PPS to this penalty was found to be 0.08 dB.

The semiconductor optical amplifier (SOA) plays an important role in the development of the all-optical signal processing because of the advantages of simple structure, easy integration and strong non-linearity. Especially the nonlinear polarization rotation effect of SOA is receiving considerable interest by many researchers nowadays. The all-optical flip-flop using the properties of SOA also obtains widespread attention by researchers, as all-optical flip-flop is an important part in the field of all-optical signal processing. In this paper, a new all-optical flip-flop structure using polarization switch (PSW) based on polarization rotation effect of SOA is presented. The main work of the paper is the simulation of all-optical logic gates and optical SR latch. The logic gate setup only uses one SOA, but it can get two different logic gates through a simulation. The extinction ratio of the logic gate is about 30dB. The structure of optical SR latch utilizes the two coupled polarization rotation switch of SOA. The structure of the flip-flop is based on these two parts. To demonstrate the feasibility of the structure, we analyze two types of flip-flops, including all-optical D and T flip-flops, whose clock pulse repetition rate is 1GHz with the pulse width of 0.3ns. The quality of all-optical flip-flop in this paper is measured by the falling and rising edge time. In the simulation, the falling edge time is about 50ps, while the rising edge time is higher than the falling edge time, because the gain increases slowly to the recovery time after the decrease of the gain of SOA. The results are useful for the development of all-optical flip-flop based on SOA.

LADAR echo signal simulator is one of the most significant components of hardware-in-the-loop (HWIL) simulation systems for LADAR, which is designed to simulate the LADAR return signal in laboratory conditions. The device can provide the laser echo signal of target and background for imaging LADAR systems to test whether it is of good performance. Some key technologies are investigated in this paper. Firstly, the 3D model of typical target is built, and transformed to the data of the target echo signal based on ranging equation and targets reflection characteristics. Then, system model and time series model of LADAR echo signal simulator are established. Some influential factors which could induce fixed delay error and random delay error on the simulated return signals are analyzed. In the simulation system, the signal propagating delay of circuits and the response time of pulsed lasers are belong to fixed delay error. The counting error of digital delay generator, the jitter of system clock and the desynchronized between trigger signal and clock signal are a part of random delay error. Furthermore, these system insertion delays are analyzed quantitatively, and the noisy data are obtained. The target echo signals are got by superimposing of the noisy data and the pure target echo signal. In order to overcome these disadvantageous factors, a method of adjusting the timing diagram of the simulation system is proposed. Finally, the simulated echo signals are processed by using a detection algorithm to complete the 3D model reconstruction of object. The simulation results reveal that the range resolution can be better than 8 cm.

Because of its aerodynamic diameter of the aerosol particles are stranded in different parts of different human respiratory system, thus affecting human health. Therefore, how to continue to effectively monitor the aerosol particles become increasingly concerned about. Use flight time of aerosol particle beam spectroscopy of atmospheric aerosol particle size distribution is the typical method for monitoring atmospheric aerosol particle size and particle concentration measurement , and it is the key point to accurate measurement of aerosol particle size spectra that measurement of aerosol particle flight time. In order to achieve accurate measurements of aerosol particles in time-of-flight, this paper design an ECL-TTL high-speed timer with ECL counter and TTL counter. The high-speed timer includes a clock generation, high-speed timer and the control module. Clock Generation Module using a crystal plus multiplier design ideas, take advantage of the stability of the crystal to provide a stable 500MHz clock signal is high counter. High count module design using ECL and TTL counter mix design, timing accuracy while effectively maintaining , expanding the timing range, and simplifies circuit design . High-speed counter control module controls high-speed counter start, stop and reset timely based on aerosol particles time-of-flight, is a key part of the high-speed counting. The high-speed counting resolution of 4ns, the full scale of 4096ns, has been successfully applied Aerodynamic Particle Sizer, to meet the precise measurement of aerosol particles time-of-flight.

The hardware random number generator based on the 74121 monostable multivibrators for applications in cryptographically secure distributed measurement and control systems with asymmetric resources was presented. This device was implemented on the basis of the physical electronic vibration generator in which the circuit is composed of two “loop” 74121 monostable multivibrators, D flip-flop and external clock signal source. The clock signal, witch control D flip-flop was generated by a computer on one of the parallel port pins. There was presented programmed the author's acquisition process of random data from the measuring system to a computer. The presented system was designed, builded and thoroughly tested in the term of cryptographic security in our laboratory, what there is the most important part of this publication. Real cryptographic security was tested based on the author's software and the software environment called RDieHarder. The obtained results was here presented and analyzed in detail with particular reference to the specificity of distributed measurement and control systems with asymmetric resources.

A tester for measuring face gears’ transmission error was developed based on single-flank rolling principle. The mechanical host was of hybrid configuration of the vertical and horizontal structures. The tester is mainly constituted by base, precision spindle, grating measurement system and control unit. The structure of precision spindles was designed, and rotation accuracy of the spindleswas improved. The key techniques, such as clamping, positioning and adjustment of the gears were researched. In order to collect the data of transmission error, high-frequency clock pulse subdivision count method with higher measurement resolution was proposed. The developed tester can inspect the following errors, such as transmission error of the pair, tangential composite deviation for the measured face gear, pitch deviation, eccentricity error, and so on. The results of measurement can be analyzed by the tester; The tester can meet face gear quality testing requirements for accuracy of grade 5.

This work introduces the concept of a digital Wavelength Division Multiplexed (WDM) network for small avionic and space platforms. For packaging and heat transfer efficiency, all optical wavelength sources occupy a common location. Addressable wavelengths are allocated to each receiver, which may be reached by selection or tuning of a transmitter wavelength. Individual delays may be applied to assure synchronization at each receiver. The output of each individual source wavelength is pre-modulated with a clock signal. Signal modulation is applied by passing or rejecting the clock signals. Due to the simplicity of the modulation, the control plane functions can be merged with the data plane functions. Although the concept is based on a single data rate, the digital WDM LAN concept can possibly be extended to process packet and analog payloads.

Charged Coupled Devices (CCD) are widely used in military and security applications, such as airborne and ship based surveillance, satellite reconnaissance and so on. Homeland security requires effective means to negate these advanced overseeing systems. Researches show that CCD based EO systems can be significantly dazzled or even damaged by high-repetition rate pulsed lasers. Here, we report femto - second laser interaction with CCD camera, which is probable of great importance in future. Femto - second laser is quite fresh new lasers, which has unique characteristics, such as extremely short pulse width (1 fs = 10-15 s), extremely high peak power (1 TW = 1012W), and especially its unique features when interacting with matters. Researches in femto second laser interaction with materials (metals, dielectrics) clearly indicate non-thermal effect dominates the process, which is of vast difference from that of long pulses interaction with matters. Firstly, the damage threshold test are performed with femto second laser acting on the CCD camera. An 800nm, 500J, 100fs laser pulse is used to irradiate interline CCD solid-state image sensor in the experiment. In order to focus laser energy onto tiny CCD active cells, an optical system of F/5.6 is used. A Sony production CCDs are chose as typical targets. The damage threshold is evaluated with multiple test data. Point damage, line damage and full array damage were observed when the irradiated pulse energy continuously increase during the experiment. The point damage threshold is found 151.2 mJ/cm2.The line damage threshold is found 508.2 mJ/cm2.The full-array damage threshold is found to be 5.91 J/cm2. Although the phenomenon is almost the same as that of nano laser interaction with CCD, these damage thresholds are substantially lower than that of data obtained from nano second laser interaction with CCD. Then at the same time, the electric features after different degrees of damage are tested with electronic multi meter. The resistance values between clock signal lines are measured. Contrasting the resistance values of the CCD before and after damage, it is found that the resistances decrease significantly between the vertical transfer clock signal lines values. The same results are found between the vertical transfer clock signal line and the earth electrode (ground).At last, the damage position and the damage mechanism were analyzed with above results and SEM morphological experiments. The point damage results in the laser destroying material, which shows no macro electro influence. The line damage is quite different from that of point damage, which shows deeper material corroding effect. More importantly, short circuits are found between vertical clock lines. The full array damage is even more severe than that of line damage starring with SEM, while no obvious different electrical features than that of line damage are found. Further researches are anticipated in femto second laser caused CCD damage mechanism with more advanced tools. This research is valuable in EO countermeasure and/or laser shielding applications. 2013 SPIE.

We investigate a clock enhancement technique using semiconductor optical amplifier based Mach-Zehnder interferometer (SOA-MZI) for all-optical clock recovery with numerical simulations. The simulations determine the optimal operation points of the SOA-MZI for return-to-zero (RZ) and non-return-to-zero (NRZ) inputs, achieving effective clock performance improvement.

We are developing a highly miniaturized trapped ion cl ock to probe the 12.6 GHz hyperfine transition in the 171 Yb + ion. The clock development is being funded by the Integrated Micro Primary Atomic Clock Technology (IMPACT) program from DARPA where the stat ed goals are to develop a clock that consumes 50 mW of power, has a size of 5 cm 3 , and has a long-term frequency stability of 10 -14 at one month. One of the significant challenges will be to develop miniatur e single-frequency lasers at 369 nm and 935 nm and the optical systems to deliver light to the ions and to collect ion fluorescence on a detector. Keywords: Atomic clock, UV lasers, laser spectroscopy, VCSEL 1. INTRODUCTION Precision timing is essential to many aspects of modern technology. It is of particular importance in communication and navigation systems. For example, the global positioning system (GPS) relies on an accurate timing reference located on each GPS satellite to provide the GPS signal. In systems where good long-term stability of the timing reference or clock is re quired (as is required in G PS systems), atomic clocks are used. In an atomic clock, the frequency of the clock signal is stabilized to a transition between two electronic energy levels in an atom or ion.

One of the challenges in quantum key distribution is to ensure adequate security against eavesdropping. The B92 protocol achieves this through the transmission of a strong and weak pulse, with key bits coded onto the weak pulse and channel monitoring done using the bit error rate of the strong pulse. However, the protocol also assumes synchronization between transmitter and receiver using a shared or transmitted clock signal. We propose a scheme that uses a mode locked laser for the strong pulse train, and a nonlinear four-wave mixing processes to generate the weak pulse train. The detector relies on dispersion effects in the transmission channel to delay the weak pulse relative to the strong pulse, and then use the strong pulse to gate the detection of the weak pulse. The scheme is thus self-synchronized and offers the option of additional security using four-wave-mixing processes.

In this letter, a novel simultaneous demultiplexing and clock recovery unit based on EAMs and clock recovery module is presented and experimentally demonstrated for a high speed OTDM system. The 10GHz clock signal with low jitter is extracted from 80Gbit/s and 160Gbit/s OTDM signal, and every channel of the OTDM signal is successfully demultiplexed using this unit. The power penalty is lower than 3dB at BER of 10 -9 .

The low cost and mass integration potential of CMOS integrated circuits create an attractive opportunity for investigating CMOS as an optical platform. Although silicon, as an indirect band gap material, is known for inefficient electroluminescence, silicon-based optical transmission is still a much sought after capability. This paper shows the potential of an all silicon transmission system for both clock and data transmission. By utilizing silicon light emitting diodes operating in avalanche, it is shown that a switching speed of above hundred megahertz is possible. The transmitter consists of an array of light sources, with metal light directors for improved external quantum efficiency. The array is pulsed across an optical fibre and received by an avalanche photodiode and amplifier module. Spectral results of the received signal confirm an optical component in excess of 100 MHz, were the off-chip driver circuitry and the photodiode receiver currently limit the bandwidth of the system. As the requirements for wideband data transmission are more stringent than for a narrow band clock signal, the transmission system was tested as a baseband digital communication system, with transmission speeds of up to 176 kbps. We also present eye diagrams of the received signal to prove the success of the transmission system, where transmission speed is limited to detectable optical levels versus allowable in-band noise. A refinement on these principles might lead to CMOS as a contender in high speed clock transmission as well as an alternative to III-V devices for low cost optical transmission systems.

This paper proposes a color mixing control system that provides adjustable color mixing using pulse-modulation light brightness period control while driving red-green-blue (RGB) light-emitting diodes (LED). The proposed control system includes a clock unit that provides a first clock signal and a second clock signal with a frequency lower than that of the first clock signal. Three control units are coupled to three LEDs emitting three different colors, respectively. Each control unit is operated based on the clock signals and a corresponding set of first and second reference values output to a driving pulse signal to the corresponding LED. Using four bit digital signal control, 4096 different colors and 16 gray levels can be provided by the digital pulse width modulator (DPWM) system. The system works using a single 5V power supply with a maximum clock frequency of 1MHz.

In this paper, it is tried to provide an innovative method to overcome several limitations of state of the art of logical gates and microprocessors, by implementation of micron-scaled optical gates. This technology can overcome such limitations, i.e. processing speed, heat dissipation, electromagnetic radiation and electrical noise immunity. This technology can be fully or partially feasible by substitution of common semiconductor technology with optical logic gates. By implementation of micron-scale optical fiber, optical couplers, fiber optical amplifiers, or fiber lasers, optical attenuators, optical fiber brag grating, femto-second optical lasers, and implementation of fundamental properties of optical coherent light, e.g. superposition, interference, phase delay, etc, it is possible to fabricate micron-scale universal logical gates, i.e. optical NAND gates, optical NOR gates, optical Exclusive-OR, optical exclusive-NOR gates and subsequently fabrication of sequential circuits (optical flip-flops), that all are fundamental blocks of microprocessors. Optical coherent light is produced by femtosecond lasers and is supplied to a network of micron-scaled fiber optics, fiber optical lasers, attenuators, fiber optical couplers, and finally are supplied to opto-couplers that change optical signals to electrical signals to be read by output console or to be written on memory cells. It is also possible to implement a combination of optical and semiconductor gates to decrease above mentioned limitations. The method of fabrication of optical gates is discussed in details and all necessary logical and technical aspects are provided too. The fundamental implemented aspect is superposition of coherent lights in fiber optic couplers. By implementation of femtosecond laser pulses, it is possible to reach to much higher frequencies of about hundreds to thousands of terahertz. Alternative optical method is provided here, e.g. implementation of fiber loops as clock circuit or even as an optical oscillator. By implementation of this technology, there will be one hundred years advance in respect to state of the art technology.

We propose and demonstrate all-optical format conversion from nonreturn-to-zero differential phase-shift-keying (NRZ-DPSK) to return-to-zero binary PSK (RZ-BPSK) at different bit-rates, using a tunable band-pass filter, a semiconductor optical amplifier (SOA) fiber ring laser and an SOA based Mach-Zehnder interferometer (SOA-MZI). The filter acts as the DPSK demodulator and also as the differential decoder. It converts the NRZ-DPSK into the RZ signals, which is equivalent to the data information before differential encoding. The SOA fiber ring laser is used to recover the clock signals from the demodulated RZ signals at different bit-rates. In the subsequent SOA-MZI, the RZ signal is used to modulate the recovered clock signal which is synchronous to the demodulated RZ signal. Thus, the amplitude information is encoded onto the phase of the clock signal, through cross gain modulation (XGM) and cross phase modulation (XPM) effects in the SOA-MZI. The converter can be operated at flexible bit-rates and used as the interface between long-haul WDM and OTDM systems.

In this paper, a scheme for all-optical AND gate which exploits the cross-phase modulation (XPM) effect in an asymmetric semiconductor-optical-amplifier-assisted Mach-Zehnder Interferometer (SOA-MZI) has been proposed for the first time. No additional input beam such as a clock signal or continuous light is employed in the design, which is required in other AND operations. The scheme is validated and the system performance under various parameters is investigated through numerical simulations. This logic gate is helpful for future all-optical signal processing configurations.

In this paper, we propose and experimentally demonstrate an all-optical non-return-to-zero (NRZ) to return-to-zero (RZ) format conversion using semiconductor ring laser (SRL). A 155Mb/s NRZ optical data signal is injected into the counterclockwise (CCW) direction of the SRL and an optical logic clock signal is injected to the clockwise (CW) propagation direction. The power and wavelength on both sides are adjusted so that during the 'high' level of the clock, the SRL is held to the CW direction regardless of the logic value of the corresponding data bit. The SRL will only be switched to the CCW direction when the input data is 'high' and when the clock level is 'low'. Therefore the NRZ format signal is converted to RZ format signal, with a duty cycle decided by the duty cycle of the optical clock. Extinction ratio of > 10 dB has been achieved and the scheme can also be used for all-optical 3R. Although the speed of the signal is yet limited, higher speed can be achieved with faster SRL devices.

All-optical wavelength conversion of differential phase-shift keyed (DPSK) signals based on SOA in a Mach-Zehnder interferometer (SOA-MZI) configuration is simulated and analyzed using the transfer function of MZI and a wideband dynamic model of SOA. The operation principle is analyzed and operation point selection, influence of SOA physical parameters, different signal format and operation speed are discussed in detail. The results of 10Gb/s operation show that SOA-MZI is compatible with both non-return-to-zero (NRZ) and return-to-zero (RZ) formatted signals. However, the conversion performance is sensitive to the operation point of the involved SOAs. To maximize the Q value of the demodulated conversion signal, the power and wavelength of the original DPSK signal and the probe light should be optimized to obtain approximately π phase difference between the upper and lower arms of MZI in the middle of each bit. Besides, SOA with short carrier lifetime and large linewidth enhancement factor is preferred for wavelength conversion applications. 40Gb/s operation is also simulated with SOA carrier lifetime of 100ps, and the results strongly suggests 40Gb/s operation with RZ formatted signals and relatively large input powers of the clock signal.

We demonstrate a tunable chromatic dispersion (CD) compensation technique using a semiconductor optical amplifier (SOA) and a coil of dispersion compensation fiber (DCF). Based on cross-phase modulation (XPM) in the SOA, the transient chirp of the received signal can be adjusted by tuning the drive current of the SOA and the power of clock pulse. In this way, a 10-Gbit/s tunable CD compensation setup, ranging from -40ps/nm to 60ps/nm, is realized without changing the length of the DCF.

We investigate the characteristics of 40-GHz all-optical clock recovery based on a distributed Bragg reflector (DBR) self-pulsating laser. With the injection of a low timing jitter clock signal, the timing jitter characteristics of the DBR self-pulsating laser are investigated using both time domain and frequency domain methods. The results reveal that the cause of the timing jitter in the recovered clock signal depends on the injected clock signal power. The system performance of the clock recovery is investigated by the injection of a 40 Gb/s return-to-zero on-off key (RZ-OOK) signal with a 2 31 - 1 pseudo random bit sequence (PRBS) pattern.

The end-resonance clock uses strong hyperfine end transition to stabilize the frequency of the local oscillator. Comparing to the conventional 0-0 atomic clock, end resonance has very small spin-exchange broadening effect. The spin-exchange rate is proportional to the number density of the alkali-metal atoms. By using the end resonance, we are able to use very high dense vapor to obtain a much better signal to noise ratio. On the other hand, the end resonance suffers from the first-order magnetic field dependence. This problem, however, can be solved by simultaneously using a Zeeman end resonance to stabilize the magnetic field. Here, we report the most recent result of the end-resonance clock. In addition, we report a whole new technique, push-pull laser-atomic oscillator, which can be thought as all-photonic clock. This new clock requires no local oscillator. It acts like a photonic version of maser, which spontaneously generates modulated laser light and modulated voltage signals. The modulation serves as the clock signal, which is automatically locked to the ground-state hyperfine frequency of alkali-metal atoms.

It is the closest technology to practice in the quantum communication at present to apply single-photon scheme to implement the quantum key distribution (QKD), and may achieve the absolute security in principle. Because of the limit of the response speed of the present single-photon detector, the code rate is still too low to come into practical use. The paper has put up a new idea to design a quick single-photon detector with a multi-port optic-fiber splitter or an optical switch array and many avalanche photo diodes (APD). All of the ports with APD work on time division and cooperate with the logic discrimination and deciding unit by the clock signal, thus the quick detection can come true to high repetition-rate pulses with a single photon. The multiple of the detection rate is decided by the number of the port. The optoelectronic integration can be adopted for the reliable detector. The applying of this detector will largely raise the code rate of the QKD, and stimulate the commercial use.

Micro-satellite is characterized by miniaturized structure and low cost, so it is a good choice to use area array CCD space camera as image system on micro-satellite. FT-18 is a monochrome frame transfer image sensor offering 1024×1024 pixels with excellent antiblooming and variable electronic shuttering. The main components of driving circuit for FT-18 include power supply unit, microcontroller unit, clock signal generator unit, and analog-to-digital (A/D) converter. The microcontroller unit controls startup sequence of all voltage, the exposure time of CCD and the working status of A/D converter; the clock signal generator unit generates sequence signals for CCD and A/D converter; the A/D converter converts the output of FT-18 to a 12-bit digital output. Special attention should be paid to the reliability of this camera for it will work in a condition different from ground. The camera may suffer from vacuum discharge, particle radiation, strong shock, hypergravity and so on. All these should be considered in the design of space camera, and enough environment tests should be done to ensure it can work normally in space.

We demonstrate a simple configuration for clock recovery from nonreturn-to-zero (NRZ) signal, which is preprocessed by a narrow-band filter. Clock component is enhanced evidently after the filter. Compared with previous preprocessing schemes, the single filter is simple and suitable for different bit-rates. The output performances related to the bandwidth and the detuning of the filter are analyzed. By cascading a clock recovery unit with semiconductor optical amplifier based fiber ring laser, clock signal can be extracted from the preprocessed signal with extinction ratio over 10 dB and root mean square timing jitter of 900 fs, at 10 to 40 Gb/s. By simply using a filter with larger bandwidth, much higher bit-rate operation can be achieved easily.

We investigated the property of conversion between phase modulation (PM) and amplitude modulation (AM) in optical fiber transmission link due to chromatic dispersion (CD) for the purpose of clock information generation. As a result, a novel all-optical clock recovery (CR) scheme from 10 Gbps non-return-to-zero differential phase-shift-keying (NRZ-DPSK) signal has been demonstrated experimentally. We introduce a chromatic dispersion induced clock tone from the NRZ-DPSK signal and feed it into a free-running semiconductor optical amplifier (SOA) based fiber ring laser to achieve an injection mode-locking. The generated mode-locked pulse is the corresponding regenerated clock of the original signal. Since no special component is required for NRZ-DPSK demodulation, our proposed method is very promising because of its simple configuration and higher stability. In experiments, 20km standard single mode fiber is employed to accumulate CD and generate PM-AM conversion hence regenerate clock tone of the NRZ-DPSK signal. The recovered clock signal with the extinction ratio over 15 dB and the root-mean-square timing jitter of 720 fs is achieved under 231-1 pseudorandom binary sequence NRZ-DPSK signals measurement. We also demonstrated a similar CR system by using a chirped fiber Bragg grating (CFBG) as the dispersion device. With the same operation principle, it is quite convenient and promising to extend our configuration to implement all-optical CR for NRZ-DPSK signal with data rate up to 40Gbps.© (2007) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The ACES (as Atomic Clock Ensemble in Space) mission, managed by the European Space Agency, has three main objectives. The first one deals with the operation and study of the laser cooled cesium clock PHARAO (as Projet d'Horloge Atomique a Refroidissement d'Atomes en Orbite) to reach a frequency accuracy of 10 -16 in space. The second one is to perform fundamental metrology by comparing the clock signal with ground based clocks via a two way time transfer link. The third one is to perform fundamental physics tests such as a new measurement of the red shift at 2 parts per million and a search for variations of fundamental physical constants. The expected time transfer resolution is 0.3 ps at 300 seconds and 7 ps per day. An H-maser developed by the Observatoire Cantonal de Neuchatel is the second ACES clock and will be used as a stable frequency reference for mid term duration. We give an overview of the ACES mission and its operation and present the first results obtained with the engineering model of the laser cooled cesium clock PHARAO. This model is first developed to validate the flight model design.

Sophisticated modulation formats like phase shift keying (PSK) as discussed for high-speed fiber-optic transmission systems operating at 40 Gbit/s and beyond, cause new challenges for clock recovery. Whereas conventional return-to-zero on-off keyed (RZ-OOK) modulated signals provide proper clock tones which can be used to recover the clock signal, the additional phase modulation (RZ-PSK) changes the spectral composition of the signal and weakens or suppresses the clock tones. This effect is bit pattern dependent as can be seen from a simple example: If all the pulses in an RZ-PSK signal are in phase, the result is equivalent to an ordinary RZ on-off-keying (OOK) signal with a strong carrier and clock tones. If the pulses in a sequence oscillate in phase by p, the result is equivalent to the well-known carrier-suppressed return-to-zero signal (CS-RZ) where the carrier is suppressed and where clock tones are differently spaced compared to RZ-OOK. In this paper we present results of the simulation of the different cases taking into account realistic bit sequences and analyze the results with special emphasis on the influence the effect has on clock recovery.

We investigated ultrafast optical signal processing schemes utilizing mode-locked semiconductor laser diodes (MLLDs) for optical time-division multiplexing (OTDM) transmission at over 100 Gbit/s and developed a polarization-insensitive all-optical clock recovery scheme for an optical-electrical hybrid phase-locked loop (PLL) operating at 160 Gbit/s. In this scheme, the MLLD functions as a voltage-controlled oscillator to which the error signal is fed back by forming a closed loop with a semiconductor optical amplifier (SOA) used as a phase comparator and with a low-frequency component used as a filter. Cross-gain modulation in the SOA enables high-frequency PLL operation at 160 Gbit/s. A bulk active layer in the SOA with small polarization dependency is the origin of the polarization insensitive clock extraction. Testing of all-optical clock extraction on an OTDM transmission test bed of 254-km field-installed fibers (Dojima-Keihanna, 63.5 km, and four spans) at 160 Gbit/s showed that the measured root-mean-square timing jitter of the recovered clock signal was as low as 240 fs. This clock extraction scheme is thus practical for use in OTDM systems operating at over 100 Gbit/s.

Future network will include wavelength division multiplexing (WDM) and optical time division multiplexing (OTDM) technologies. All-optical format conversion between their respective preferable data formats, non-return-to-zero (NRZ) and return-to-zero (RZ), may become an important technology. In this paper, 10Gbit/s all-optical NRZ-to-RZ conversion is demonstrated based on terahertz optical asymmetric demultiplexer (TOAD) using clock all-optically recovered from the NRZ signal for the first time. The clock component is enhanced in an SOA and the pseudo-return-to-zero (PRZ) signal is filtered. The PRZ signal is input into an injection mode-locked fiber ring laser for clock recovery. The recovered clock and the NRZ signal are input into TOAD as pump signal and probe signal, respectively, and format conversion is performed. The quality of the converted RZ signal is determined by that of the recovered clock and the NRZ signal, whereas hardly influenced by gain recovery time of the SOA. In the experimental demonstration, the obtained RZ signal has an extinction ratio of 8.7dB and low pattern dependency. After conversion, the spectrum broadens obviously and shows multimode structure with spectrum interval of 0.08nm, which matches with the bit rate 10Gbit/s. Furthermore, this format conversion method has some tolerance on the pattern dependency of the clock signal.

40Gbit/s all-optical 3R regeneration was demonstrated. The wavelength of the data signal was converted with an SOA by cross-gain modulation (XGM). The clock recovery was based on Fabry-Perot (F-P) filter of high finesse (F=1000). The actual bit rate of the data signal was 40.04796Gbit/s, matching the free spectral range (FSR) of the F-P filter. Two SOAs were used in series as the decision gate to make full use of the nonlinearity. Taking advantage of the chirp, one narrowband OBF was used to reshape the waveforms in the clock recovery, so as to reduce the pattern effect. Another narrowband OBF was used after the decision gate to diminish the tails of the pulses. The clock signal had a root mean square (RMS) timing jitter of around 843fs. The output data signal of the regenerator had an optical signal-to-noise ratio (OSNR) of more than 40dB/0.1nm. The maximum timing jitter was 1.439ps.

An improved scheme for all-optical pulse decision gating by cross-gain modulation(XGM) in semiconductor optical amplifier (SOA) is shown in this paper. Influences of the property of optical clock pulses (including the pulse extinction ratio (ER) and the power) on the shape of regeneration pulse of this optical decision gate are studied by means of numerical simulation and experiment. The power and extinction ratio of optical clock pulses are adjusted in the process of numerical simulation. In the beginning, with the power of clock pulses rising or ER dropping, the pattern of the regeneration pulse gets better and the "1" code noise comes down. There are optimal values of the power and ER of clock pulse for the best pattern of the output pulses. If the ER continues to decrease, the ER of output pulses dropped. Similarly, if the power of clock pulse continues to increase the pattern of the regeneration pulse gets worse. In experiment of optical decision, 40Gb/s regenerated pseudo random bit-sequence (PRBS) data signal was got from degraded PRBS input signal and recovery clock pulses by passing the optical decision gating. The result of experiment is uniform in the numerical simulation.

A novel scheme for all-optical frequency multiplication/recovery based on the semiconductor optical amplifier (SOA) ring cavity is proposed and investigated numerically. The results show, for a 2.5GHz driving pulse train, it can be generated 5-25GHz repetition rate pulse trains with low clock amplitude jitter (CAJ), polarization independence and high peak power. Furthermore, the extraction of the clock signal from a pseudorandom bit sequence (PRBS) signal can be realized based on the proposed scheme.

To improve the all-optical clock recovery, a novel device termed as code mixer was designed to preprocess the injected data signals. In the time domain, the code mixer can change the probability distribution of the amplitude of the data pulses and reduce the amount of codes "0". In the power spectrum, the code mixer can reduce the continuous spectral component. It was demonstrated experimentally that the code mixer could concentrate the probability distribution of the amplitude of the pulses to half of the maximum amplitude. It was also demonstrated theoretically and experimentally that using a code mixer of more ways or several cascade code mixers the clock signal recovered can be further improved. In the experiment of 40GHz all-optical clock recovery using an injection mode-locked fibre ring laser based on a semiconductor optical amplifier, the amplitude fluctuation and timing jitter of the clock pulses recovered caused by the pattern effect were reduced obviously.

We describe an in-service dispersion monitoring technique which we call dithered-filter method and show its application to adaptive dispersion compensation. In the proposed method, we filter out a portion of the received signal light by a dithered optical band-pass filter and derive the accumulated dispersion from the phase shift of the extracted clock signal. This method does not require any modification of the transmitter, and is applicable to any modulation format as far as the clock signal is extracted. In addition, owing to the dithering and the synchronous detection, high accuracy is realized with a short measurement time less than 200 msec. In this paper, we explain the principle of operation of the proposed method and show the experimental demonstration of fast adaptive dispersion compensation in a 40 Gbit/s reconfigurable optical network.

In this work, we demonstrate clock recovery from a patterned 160Gb/s optical-time-division-multiplexed (OTDM) return-to-zero (RZ) data stream. A cascaded LiNbO 3 Mach-Zehnder modulator is employed as an efficient optical-electrical mixer. A phase-locked-loop (PLL) is used to lock the cross-correlation component between the optical signal and a local oscillating signal. As a result, clock signal at 10GHz is extracted from the 160Gb/s optic al TDM signal. The measured root-mean-square (RMS) timing jitter of the 10GHz clock signal is ~ 130 fs. Keywords : Clock Recovery, Cascaded Modulator INTRODUCTION In ultra high speed optical communication networks, clock recovery is an essential element for any optical access node because it synchronizes the receiver decision circuitry with the incoming data stream 1 . Therefore, a stable clock source with low jitter characteristic 2 at the receiver end is required. However, due to the speed limitation of electrical circuits, at data rates beyond ~ 40 Gb/s, it becomes increasingly difficult to perform the stable clock recovery electronically. Optical clock recovery techniques that can be scaled to data rates of many tens of Gb/s to > 100 Gb/s will be a prerequisite to high data rate communication links of the future. For the optical clock recovery systems, the key steps are Optical-Electric (OE) mixing and cross-correlation detection. One approach to high-speed clock extraction is the injection mode locking technique, in which optical clock signal is obtained by launching the pulse trains into the cavity of a self-pulsating laser

We propose a new optical data storage system with minute spheres. To avoid a problem of jitter as instability of rotating disk speed and fluctuation of recording bit formation, we have devised a new process. The process involves the use of dye-doped minute spheres arranged upon a surface-relief structure as recording bits. Alternate laminating recordable sphere layer with sensitivity and buffer layer with insensitivity structurally limits recording bits in three dimensions. We can limit a sensitive region within a sphere diameter. A reflection-type confocal optical microscope can read out both bit signals and shape signals from minute spheres at high resolution. Confocal relection of ~10% was measured before and after recording from a single minute sphere with Spiropyran as a recording dye. Also, the shape signal from each minute sphere is utilized as a clock signal in recording and readout. The clock signal can be produced by separating a high-level signal and a low-level signal on the basis of a threshold. In our minute-sphere optical storage system, a shift between positions of the recording bit and the clock signal does not occur because the clock signal is generated based on the shape signal from a minute sphere as the recording bit. This jitter-free technique proved to be extremely effective for disk recording and readout.

Nowadays, there exist a high number of commercial FPGA prototype boards. Nevertheless, these boards are basically oriented to functional verification of synchronous designs. So, it would be interesting to include tests modules dedicated to characterization of digital circuits. These circuits have not to be limited to synchronous circuits, but asynchronous circuits will also be considered due to their potential advantage. Among parameters to characterization, we are going to include the latency, throughput, power consumption and noise. One of the missions of this characterization will be the comparison among synchronous and asynchronous implementations. In most of existent boards, the measure of certain merit parameters of the design is hindered by the impossibility of varying the frequency of the clock signal, or for the inexistence of measuring points of power consumption or high-speed signals. The main novelty that contributes the design of this board is the possibility of extracting dynamic parameters of the design operation implemented on FPGA. In this work, a prototype board based on FPGA is proposed. One of the main novelty is the inclusion of an autonomous test system permitting functional verification and characterization of implemented designs. As an application, a test bench has been developed in order to compare and validate several arithmetic circuits, including synchronous and asynchronous implementations.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Complexity of clock generator is one of the most important parameters in the design and optimization of switched-capacitor (SC) finite impulse response (FIR) filters. There are different SC FIR filter architectures. Some of them need a simple clock generator but the others require a quite complicated multiphase clock system. In the latter case an external clock system (i.e., outside the integrated circuit) is unrealistic because of a great number of the required external pins. We have implemented various SC FIR filter architectures together with complex internal clock generators in the CMOS 0.8 μm and 0.35 μm technologies. One of the most important problems in the design process was the optimization of waveforms and widths of the clock impulses. SC FIR filters are very sensitive to parameters of clock systems. Thus the clock generators must be designed very precisely. We demonstrate results of the design of the 64-phase clock generator for a programmable rotator SC FIR filter. In our approach the width of the clock impulses is controlled by two external signals. This is a very convenient solution, because optimization of the clock impulses, which was difficult in other approaches, is currently much easier. The internal clock generator area is ca. 0.15 mm 2 in the CMOS 0.35 μm technology, i.e., only 7 % of the entire SC FIR filter chip area.

In this paper, we demonstrate clock recovery from a patterned 160Gb/s optical-time-division-multiplexed (OTDM) return-to-zero (RZ) data stream. A cascaded LiNbO3 Mach-Zehnder modulator is employed as an efficient optical-electrical mixer. A phase-locked-loop (PLL) is used to lock the cross-correlation component between the optical signal and a local oscillating signal. As a result, clock signal at 10GHz is extracted from the 160Gb/s optical TDM signal. The measured root-mean-square (RMS) timing jitter of the 10GHz clock signal is ~ 130fs.

The purpose of this paper is to describe the conception of the detectors developed for a system dedicated to quantum keys distribution on optical fiber network. Because there is still no commercial single photon sources quantum keys distribution is usually based on faint laser pulses transmission. Detection of such signals is very difficult but it can be improved by the use of a clock signal. Detectors based on APD can be designed to use this clock signal. In order to have a very good synchronization of both quantum keys and clock signals it is necessary to minimize chromatic dispersion in the optical fibers. The innovation presented in this paper is to use modulators effects leading to a very small change in the wavelength of the modulated signal. So it is possible to get two very close wavelengths dedicated to both signals, avoiding dispersion in the optical fiber. The system is designed at the 1.55 μm and is based on an acousto-optic modulator and an optical filter to separate both wavelengths at the reception. The detector is realized with an InGaAs APD, working in gated mode at liquid nitrogen temperature in order to reduce dark counts.

An all-optical full adder using semiconductor optical amplifiers has been demonstrated at 10 Gbps for the first time. The full adder consisted of XOR and NOR gates only utilizes the mechanism of cross-gain modulation. The full adder utilize two logic functions of SUM and CARRY, which can be demonstrated by using two XOR gates and four NOR gates, respectively. By passing signal A as probe signal and signal B as pump signal into SOA-1, Boolean A NOT B can be obtained. Also, by changing the role of signals A and B for SOA-2, Boolean NOT A B can be acquired. Addition of Boolean A NOT B and NOT A B results in NOT A B + A NOT B , which is Boolean expression of logic XOR. By passing this XOR signal and signal C into the second XOR gate with the same principle, SUM signal of the full adder can be obtained. The Boolean expression of SUM can be expressed as A # B # C . With the first three NOR gates, Boolean NOT(A+B), NOT(B+C), and NOT(C+A) can be obtained. With the addition of these outputs, Boolean NOT(A+B) + NOT(B+C) + NOT(C+A) can be formed. By injecting these outputs through the last NOR gate with clock signal, CARRY signal of the full adder can be realized. The Boolean expression of CARRY can be expressed as AB +BC +CA. The extinction ratio is about 6.1dB.

By using gain nonlinearity characteristics of semiconductor optical amplifier, an all-optical binary half adder at 10 Gbps is demonstrated. The half adder operates in single mechanism, which is XGM. The half adder utilizes two logic functions of SUM and CARRY, which can be demonstrated by using the XOR gate and the AND gate, respectively. In the XOR (A NOT B + NOT A B) gate, Boolean A NOT B is obtained by using signal A as a probe beam and signal B as a pump beam in SOA-1. Also, Boolean NOT A B is obtained by using signal B as a probe beam and signal A as a pump beam in SOA-2. By adding two outputs from SOA-1 and SOA-2, Boolean A NOT B + NOT A B (logic XOR) can be obtained. In the AND (AB ) gate, Boolean NOT B is firstly obtained by using signal B as a pump beam and clock signal as a probe beam in SOA-3. By passing signal A as a probe beam and NOT B as a pump beam through SOA-4, Boolean AB is acquired. By achieving this experiment, we also explored the possibilities for the enhanced complex logic operation and higher chances for multiple logic integration.

The current trend of exponential increases in clock frequency and an increase in the number of transistors per die causes increases in power consumption, total die area dedicated to the clock distribution network, and clock overhead incurred relative to the clock cycle time. Self-timed circuits may provide an alternative approach to synchronous circuit design that helps to reduce the negative characteristics of the high-speed clocks needed by synchronous circuits. This work presents a gate-level performance model and transistor-level performance, power and area approximations for both self-timed and static CMOS ripple-carry adders. These results show that for self-timed circuits with uniformly random input operands the average performance of a ripple-carry adder is logarithmic and improves performance by 37% with a 30% increase in the total transistor width as compared to a static CMOS ripple-carry adder.

The Anglo-Australian Observatory has developed a 2nd generation optical CCD controller to replace an earlier controller used now for almost twenty years. The new AAO2 controller builds on the considerable experience gained with the first controller, the new technologies now available and the techniques developed and successfully implemented in AAO's IRIS2 detector controller. The AAO2 controller has been designed to operate a wide variety of detectors and to achieve as near to detector limited performance as possible. It is capable of reading out CCDs with one, two or four output amplifiers, each output having its own video processor and high speed 16-bit ADC. The video processor is a correlated double sampler that may be switched between low noise dual slope integration or high speed clamp and sample modes. Programmable features include low noise DAC biases, horizontal clocks with DAC controllable levels and slopes and vertical clocks with DAC controllable arbitrary waveshapes. The controller uses two DSPs; one for overall control and the other for clock signal generation, which is highly programmable, with downloadable sequences of waveform patterns. The controller incorporates a precision detector temperature controller and provides accurate exposure time control. Telemetry is provided of all DAC generated voltages, many derived voltages, power supply voltages, detector temperature and detector identification. A high speed, full duplex fibre optic interface connects the controller to a host computer. The modular design uses six to ten circuit boards, plugged in to common backplanes. Two backplanes separate noisy digital signals from low noise analog signals.

The dynamic characteristics of an ultra-long semiconductor optical amplifier (UL-SOA) with a length of 4 mm are investigated experimentally. An optically clocked technique is applied for suppressing the patterning effects in an SOA and for exploiting effectively the fast intra-band effects. The gain dynamic in the UL-SOAs is here stabilised by a sinusoidal optical clock signal which is additionally injected into the device, bit interleaved with a PRBS data signal. The optimal operation condition of the novel scheme concerning power levels of the RZ data signal and clock signal are analysed in detail at 40 Gbit/s. We use the ultra-fast nonlinearities in the UL-SOAs for regenerating of a 40 Gbit/s data signal in amplitude, time and pulse shape. The 40 GHz recovered clock signal in the optically clocked 3R regenerator is generated by a self-pulsating three section DFB laser. An excellent regenerative performance even for strong degraded data signals is demonstrated.

Studies of electronic component stress have typically focused on temperature, humidity, and voltage stress. There has been relatively little emphasis on clock signal frequency stress. This study investigated effects of clock frequency stress on a high performance microcontroller used to control the on-off frequency of LEDs on a printed circuit board. Based on the design specification, several frequency levels between 0 and the terminal clock frequency were selected. Thermal profile samples for each stress level were collected using an infrared camera. The data were then divided into two groups for model development and evaluation. Artificial neural network and statistical regression approaches were used to model thermal profiles for each stress level. Objectives were to (1) explore impact of clock frequency stress on IC functionality, (2) observe heating rate differences under clock frequency stress over time; and (3) predict stress levels using the two approaches. Results indicate that the average prediction error is about 7.9% for the neural network approach and about 23.8% for the statistical regression approach. Future directions include thermal profile modeling using Finite Element Analysis (FEA) and development of robust hybrid analytic and experimental models for microcontroller lifetime prediction.

In this paper, we present a scheme for recovering 1 0GHz clock from 40Gb/s and 80 Gb/s time division multiplexed (TDM) return to zero (RZ) data stream. Theproposed clock recovery is successfully demonstrated using an electrical phase locked ioop (PLL). The jitter of the recovered clock is estimated to be around 5Ofs. The key part in the proposed clock recovery circuit is a LiNbO3 Mach-Zehndermodulator which is shown to be highly effective in optical to electrical down conversion. Keywords: High speed transmission, LiNbO3 modulator, Clock recovery IntroductionThe continuing demand for higher data transmission capacity will fuel the need for higher speed optical transmission system than that installed today. Systems operating at single channel speeds of 1 0Gb/s are currently being deployed. For time division multiplexed (TDM) systems, signals at low data rate are multiplexed tocreate data at a higher rate. At the receiver end, the received optical TDM pulsetrain is then demultiplexed into each lower data rate channel using varioustechniques like nonlinear optical loop mirror (NOLM) [1] and semiconductoroptical amplifier (SOA) [2] .

Digital switching noise is the main source of on-chip noise in mixed-signal ICs. When many digital gates change state together, a large cumulative current spike flows through parasitic resistances and inductances and noise is also injected into the substrate, causing the sensitive analog portions of the design to malfunction. Many solutions have been proposed to alleviate this problem from both the analog and the digital domain. Some current mode families are used in low noise applications, but are strongly unsuited for low power applications, due to its static power consumption. In this paper we propose a set of techniques to reduce the switching noise generated by the digital circuitry, based on classical digital (static CMOS) methodologies at a circuit level. One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact different solutions for the clocking logic generate very different results for switching noise. This paper faces the analysis and design of clock generation and distribution logic oriented towards low noise applications. Some illustrative examples will shown the feasibility of the proposed solutions, and some useful design guidelines will be proposed for the community of digital designers.

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.