Search

Your search keyword '"Integrated circuits -- Intellectual property"' showing total 10,878 results

Search Constraints

Start Over You searched for: "Integrated circuits -- Intellectual property" Remove constraint "Integrated circuits -- Intellectual property" Publisher newsrx llc Remove constraint Publisher: newsrx llc
10,878 results on '"Integrated circuits -- Intellectual property"'

Search Results

1. Patent Issued for Methods relating to intestinal organ-on-a-chip (USPTO 12104174)

3. Researchers Submit Patent Application, 'Field-Aware Metal Fills For Integrated Circuit Passive Components', for Approval (USPTO 20250012893)

4. Patent Application Titled 'Integrated Circuit, System, And Method For Coupling Optical Signals Into An Integrated Circuit' Published Online (USPTO 20250013087)

5. Patent Application Titled 'Integrated Circuit With Low Power Mode Management' Published Online (USPTO 20250015698)

6. Researchers Submit Patent Application, 'Adjustment Of Fpga System Design Using Language-Based Machine Learning Models', for Approval (USPTO 20250013823)

7. Patent Issued for Neural network accelerator architecture based on custom instruction and DMA on FPGA (USPTO 12190160)

8. Patent Issued for Asymmetric 8-shaped inductor and corresponding switched capacitor array (USPTO 12191342)

9. Patent Issued for Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit (USPTO 12189416)

10. Researchers Submit Patent Application, 'Storage Devices That Support Sub-Block Reclaim Operations Therein Upon Detection Of Uncorrectable Errors', for Approval (USPTO 20250014670)

11. Researchers Submit Patent Application, 'Semiconductor Structure Including Capacitor And Method For Forming The Same', for Approval (USPTO 20250016982)

12. Researchers Submit Patent Application, 'Self-Aligned Structure and Method on Interposer-based PIC', for Approval (USPTO 20250012983)

13. Researchers Submit Patent Application, 'Method For Stacking Integrated Circuit Wafers And Dies', for Approval (USPTO 20250015045)

14. Researchers Submit Patent Application, 'Method For Producing A Package For A Semiconductor Chip, Package For A Semiconductor Chip And Semiconductor Device', for Approval (USPTO 20250014970)

15. Researchers Submit Patent Application, 'Integrated Power Device With Energy Harvesting Gate Driver', for Approval (USPTO 20250015707)

16. Researchers Submit Patent Application, 'High-Voltage Gate Driver Integrated Circuit Using Galvanic Isolator', for Approval (USPTO 20250015077)

17. Patent Application Titled 'Semiconductor Integrated Circuit, Semiconductor Device And Method For Aligning Semiconductor Integrated Circuits' Published Online (USPTO 20250015012)

18. Patent Application Titled 'Semiconductor Device Structure Including Fuse Structure Embedded In Substrate' Published Online (USPTO 20250017002)

20. 'Nonvolatile Memory Devices And Memory Packages Including The Same' in Patent Application Approval Process (USPTO 20250014645)

21. 'Integrated Circuit Memory Devices Having Highly Integrated Memory Cells Therein With Enhanced Landing Pad Structures' in Patent Application Approval Process (USPTO 20250016981)

22. 'Integrated Circuit Memory Devices Having Enhanced Memory Cell Layouts' in Patent Application Approval Process (USPTO 20250016991)

23. Researchers Submit Patent Application, 'Clock Doubler, A Clock Generating Device And A Semiconductor System Using The Same', for Approval (USPTO 20250015786)

24. Patent Issued for Transmitting a response with a request and state information about the request (USPTO 12189544)

26. Patent Issued for Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames (USPTO 12192079)

27. Patent Application Titled 'Sampling Circuit, Method for Using Sampling Circuit, Storage Medium, and Electronic Device' Published Online (USPTO 20250015812)

28. Patent Application Titled 'Memory Device Comprising Memory Cells Storing Calibration Data And Operating Method Thereof' Published Online (USPTO 20250014620)

29. Patent Issued for Microchip and sample sorting kit (USPTO 12180440)

30. Patent Application Titled 'Integrated Inductor Including Magnetic Layer' Published Online (USPTO 20250006631)

31. Researchers Submit Patent Application, 'Programmable Delay Testing Circuit', for Approval (USPTO 20250004048)

33. Patent Application Titled 'Power Stage Safety And Latch-Up Prevention In Multi-Phase Dc-Dc Converter By Ensuring Safe Pwm Sequencing' Published Online (USPTO 20250007390)

34. Patent Application Titled 'Position Detector, Integrated Circuit, And Position Detection Method' Published Online (USPTO 20250004587)

35. Patent Application Titled 'Apparatus For Separating Singulated Die From Substrate Dicing Tape And Methods Of Using The Same' Published Online (USPTO 20250006520)

37. 'Phase Aligning Multiple Channel Dividers Without Stopping Vco Root Clock' in Patent Application Approval Process (USPTO 20250007522)

38. 'Inter-Integrated Circuit (I²c) Interface With Device Address Used For Device Configuration' in Patent Application Approval Process (USPTO 20250004977)

39. 'Control Integrated Circuit For Controlling An Operating Device For Lighting Means; Operating Device; Luminaire And Method For Operating A Control Integrated Circuit' in Patent Application Approval Process (USPTO 20250008622)

40. 'Adaptive Refresh Rate Generator' in Patent Application Approval Process (USPTO 20250006245)

41. Patent Issued for Manipulation zone for qubits in quantum dots (USPTO 12182041)

42. Patent Issued for Embedded processor architecture with shared memory with design under test (USPTO 12182485)

43. Patent Issued for Color selection schemes for storage allocation (USPTO 12182549)

44. Patent Application Titled 'Timing Constraint Auto-Creation For Integrated Circuit Testing' Published Online (USPTO 20250005244)

45. Researchers Submit Patent Application, 'Semiconductor Packages With Multiple Types Of Conductive Components', for Approval (USPTO 20250006585)

46. Researchers Submit Patent Application, 'Method For Improving Fdsoi Device Leakage', for Approval (USPTO 20250006743)

47. Researchers Submit Patent Application, 'Double-Sided Polishing Of Semiconductor Wafers With Dynamic Control', for Approval (USPTO 20250001546)

48. Researchers Submit Patent Application, 'Double-Sided Integrated Circuit With Damage Sensor', for Approval (USPTO 20250006629)

49. Researchers Submit Patent Application, 'Component Having An Integrated Converter Layer And Method For Producing A Component', for Approval (USPTO 20250007237)

50. Patent Application Titled 'Semiconductor Packages With Multiple Types Of Conductive Components' Published Online (USPTO 20250006685)

Catalog

Books, media, physical & digital resources