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We used density functional theory with a hybrid functional to investigate the structure and properties of [4H]Si (hydrogarnet) defects in α-quartz as well as the reactions of these defects with electron holes and extra hydrogen atoms and ions. The results demonstrate the depassivation mechanisms of hydrogen-passivated silicon vacancies in α-quartz, providing a detailed understanding of their stability, electronic properties, and behaviour in different charge states. While fully hydrogen passivated silicon vacancies are electrically inert, the partial removal of hydrogen atoms activates these defects as hole traps, altering the defect states and influencing the electronic properties of the material. Our calculations of the hydrogen migration mechanisms predict the low energy barriers for H+, H0, and H−, with the lowest barrier of 0.28 eV for neutral hydrogen migration between parallel c-channels and a similar barrier for H+ migration along the c-channels. The reactions of electron holes and hydrogen species with [4H]Si defects lead to the breaking of O–H bonds and the formation of non-bridging oxygen hole centres (NBOHCs) within the Si vacancies. The calculated optical absorption energies of these centres are close to those attributed to individual NBOHCs in glass samples. These findings can be useful for understanding the role of [4H]Si defects in bulk and nanocrystalline quartz as well as in SiO2-based electronic devices. [ABSTRACT FROM AUTHOR]

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (V t h) and gate leakage current (I g s s) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in S i O 2 caused by oxide electric field (E o x)  stress affect the V t h of SiC MOSFETs. The saturation and turnaround behavior of the V t h shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The I g s s under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of V t h shift and I g s s under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. [ABSTRACT FROM AUTHOR]

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium–tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility. [ABSTRACT FROM AUTHOR]

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed. [ABSTRACT FROM AUTHOR]

Crystalline calcium fluoride (CaF2) is drawing significant attention due to its great potential of being the gate dielectric of two-dimensional (2D) material MOSFETs. It is deemed to be superior to boron nitride and traditional silicon dioxide (SiO2) because of its larger dielectric constant, wider band gap, and lower defect density. Nevertheless, the CaF2-based MOSFETs fabricated in the experiment still present notable reliability issues, and the underlying reason remains unclear. Here, we studied the various intrinsic defects and adsorbates in CaF2/molybdenum disulfide (MoS2) and CaF2/molybdenum disilicon tetranitride (MoSi2N4) interface systems to reveal the most active charge-trapping centers in CaF2-based 2D material MOSFETs. An elaborate Table comparing the importance of different defects in both n-type and p-type devices is provided. Most impressively, the oxygen molecules (O2) adsorbed at the interface or surface, which are inevitable in experiments, are as active as the intrinsic defects in channel materials, and they can even change the MoSi2N4 to p-type spontaneously. These results mean that it is necessary to develop a high-vacuum packaging process, as well as prepare high-quality 2D materials for better device performance. [ABSTRACT FROM AUTHOR]

The majority of voltage-gated ion channels contain a defined voltage-sensing domain and a pore domain composed of highly conserved amino acid residues that confer electrical excitability via electromechanical coupling. In this sense, the voltage-gated proton channel (Hv1) is a unique protein in that voltage-sensing, proton permeation and pH-dependent modulation involve the same structural region. In fact, these processes synergistically work in concert, and it is difficult to separate them. To investigate the process of Hv1 voltage sensor trapping, we follow voltage-sensor movements directly by leveraging mutations that enable the measurement of Hv1 channel gating currents. We uncover that the process of voltage sensor displacement is due to two driving forces. The first reveals that mutations in the selectivity filter (D160) located in the S1 transmembrane interact with the voltage sensor. More hydrophobic amino acids increase the energy barrier for voltage sensor activation. On the other hand, the effect of positive charges near position 264 promotes the formation of salt bridges between the arginines of the voltage sensor domain, achieving a stable conformation over time. Our results suggest that the activation of the Hv1 voltage sensor is governed by electrostatic–hydrophobic interactions, and S4 arginines, N264 and selectivity filter (D160) are essential in the Ciona-Hv1 to understand the trapping of the voltage sensor. [ABSTRACT FROM AUTHOR]

This study focuses on InGaZnO-based synaptic devices fabricated using reactive radiofrequency sputtering deposition with highly uniform and reliable multilevel memory states. Electron trapping and trap generation behaviors were examined based on current compliance adjustments and constant voltage stressing on the ITO/InGaZnO/ITO memristor. Using O2 + N2 plasma treatment resulted in stable and consistent cycle-to-cycle memory switching with an average memory window of ~95.3. Multilevel resistance states ranging from 0.68 to 140.7 kΩ were achieved by controlling the VRESET within the range of −1.4 to −1.8 V. The modulation of synaptic weight for short-term plasticity was simulated by applying voltage pulses with increasing amplitudes after the formation of a weak conductive filament. To emulate several synaptic behaviors in InGaZnO-based memristors, variations in the pulse interval were used for paired-pulse facilitation and pulse frequency-dependent spike rate-dependent plasticity. Long-term potentiation and depression are also observed after strong conductive filaments form at higher current compliance in the switching layer. Hence, the ITO/InGaZnO/ITO memristor holds promise for high-performance synaptic device applications. [ABSTRACT FROM AUTHOR]

This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs. [ABSTRACT FROM AUTHOR]

Rather than generating a photocurrent through photo-excited carriers by the photoelectric effect, the photogating effect enables us to detect sub-bandgap rays. The photogating effect is caused by trapped photo-induced charges that modulate the potential energy of the semiconductor/dielectric interface, where these trapped charges contribute an additional electrical gating-field, resulting in a shift in the threshold voltage. This approach clearly separates the drain current in dark versus bright exposures. In this review, we discuss the photogating effect-driven photodetectors with respect to emerging optoelectrical materials, device structures, and mechanisms. Representative examples that reported the photogating effect-based sub-bandgap photodetection are revisited. Furthermore, emerging applications using these photogating effects are highlighted. The potential and challenging aspects of next-generation photodetector devices are presented with an emphasis on the photogating effect. [ABSTRACT FROM AUTHOR]

Gray scale consistency in pixels was extremely important for electrowetting displays (EWDs). However, traditional electrowetting display driving waveforms could not obtain a pixel aperture ratio consistency, which led to the occurrence of gray inconsistency even if it was the same driving waveform. In addition, the oil backflow caused by charge trapping could not be sustained. Therefore, a multi-direct current (DC) overdriving waveform for gray scale consistency was proposed in this paper, which could effectively improve the performance of EWDs. The driving waveform was divided into a start-up driving phase and a stable driving phase. The stable driving phase was composed of a square wave with a duty cycle of 79% and a frequency of 43 Hz. Subsequently, an overdriving pulse was also introduced in the stable driving phase. The multi-DC driving waveform for gray scale consistency was applied to a thin film transistor-electrowetting display (TFT-EWD). The average difference between increasing driving voltage and decreasing driving voltage was only 2.79%. The proposed driving waveform has an aperture ratio of 3.7 times at low voltages compared to DC driving. [ABSTRACT FROM AUTHOR]

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET. [ABSTRACT FROM AUTHOR]

Field-effect transistors based on organic semiconducting materials (OFETs) have unique advantages of intrinsically mechanical flexibility, simple preparation process, low manufacturing cost, and large-area preparation. Through the innovation of new material design and device structures, the performance of device parameters such as mobility, on–off current ratio, and the threshold voltage (VTH) of OFETs continues to improve. However, the VTH shift of OFETs has always been an important problem restricting their practical applications. In this work, we observe that the VTH of polymer OFETs with the widely investigated device structure of a SiO2 bottom-gate dielectric is noticeably shifted by pre-applying a large gate voltage. Such a shift in VTH remains to a large extent, even after modifying the surface of the SiO2 dielectric using a hexamethyldisilazane (HMDS) self-assembled monolayer. This behavior of VTH can be ascribed to the charge trappings at the bulk of the SiO2. In addition, the generality of this observation is further proven by using two other conjugated polymers including p-type PDPP3T and n-type PTzNDI-2FT, and a similar trend is obtained. [ABSTRACT FROM AUTHOR]

Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM. [ABSTRACT FROM AUTHOR]

The radiation response of Al2O3 on silicon substrate under gamma-rays is studied in this article. The atomic layer deposited Al2O3 based metal-oxide-semiconductor structures were irradiated under gamma-ray with the total dose of 1.2 Mrad(Si)/2.5 Mrad(Si)/4 Mrad(Si). The generation, transportation and trapping characteristics of radiation induced charges were studied by using electronic, physical and chemical methods. Firstly, the radiation induced trapped charge density in Al2O3 is up to 1012 cm−2, with the effective trapping efficiency of 7–20% under irradiation. Secondly, the leakage current through Al2O3 changes little with the increase of radiation total dose. Thirdly, oxygen vacancy in Al2O3 and O dangling bonds and Al-Si metallic bonds at Al2O3/Si interface are dominant radiation induced defects in Al2O3/Si system, and the valence band offset between Al2O3 and Si is found to decrease after irradiation. From the results we can see that Al2O3 is radiation resistant from the aspect of leakage current and crystallization characteristics, but the radiation induced charge trapping and new defects in Al2O3/Si structure cannot be ignored. This paper provides a reference for the space application of Al2O3 based MOS devices. [ABSTRACT FROM AUTHOR]

Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials. [ABSTRACT FROM AUTHOR]

Charge trapping effects represent a major challenge in the performance evaluation and the measurement-based compact modeling of modern short-gate-length (i.e., ≤0.15 μm) Gallium Nitride (GaN) high-electron mobility transistors (HEMT) technology for millimeter-wave applications. In this work, we propose a comprehensive experimental methodology based on multi-bias large-signal transient measurements, useful to characterize charge-trapping dynamics in terms of both capture and release mechanisms across the whole device safe operating area (SOA). From this dataset, characterizations, such as static-IV, pulsed-IV, and trapping time constants, are seamlessly extracted, thus allowing for the separation of trapping and thermal phenomena and delivering a complete basis for measurement-based compact modeling. The approach is applied to different state-of-the-art GaN HEMT commercial technologies, providing a comparative analysis of the measured effects. [ABSTRACT FROM AUTHOR]

The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In0.7Ga0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks was investigated. The equivalent field across the multi-gate stacks was compared with a single layer used to compare the instability of electrical characteristics. The observed threshold voltage degradation (ΔVT) was consistent with the phenomenon of fast transient trapping of injected electrons at pre-existing shallow defects in the high-κ dielectric of HfO2, in which this charging was recovered by applying a relaxation voltage. Excluding the fast-transient charging components, the power law exponent (n), with respect to the time-dependent threshold voltage degradation, ranged from 0.3 to 0.35 for both single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks. This long-term (slow) VT shift, which was strongly correlated with transconductance (Gm) degradation, was attributed to significant charge trapping in the border trap or/and defect sites within the high-κ dielectric. [ABSTRACT FROM AUTHOR]

In this study, the impact of the type of ligand at the surface of colloidal CdSe@CdS dot-in-rod nanostructures on the basic exciton relaxation and charge localization processes is closely examined. These systems have been introduced into the field of artificial photosynthesis as potent photosensitizers in assemblies for light driven hydrogen generation. Following photoinduced exciton generation, electrons can be transferred to catalytic reaction centers while holes localize into the CdSe seed, which can prevent charge recombination and lead to the formation of long-lived charge separation in assemblies containing catalytic reaction centers. These processes are in competition with trapping processes of charges at surface defect sites. The density and type of surface defects strongly depend on the type of ligand used. Here we report on a systematic steady-state and time-resolved spectroscopic investigation of the impact of the type of anchoring group (phosphine oxide, thiols, dithiols, amines) and the bulkiness of the ligand (alkyl chains vs. poly(ethylene glycol) (PEG)) to unravel trapping pathways and localization efficiencies. We show that the introduction of the widely used thiol ligands leads to an increase of hole traps at the surface compared to trioctylphosphine oxide (TOPO) capped rods, which prevent hole localization in the CdSe core. On the other hand, steric restrictions, e.g., in dithiolates or with bulky side chains (PEG), decrease the surface coverage, and increase the density of electron trap states, impacting the recombination dynamics at the ns timescale. The amines in poly(ethylene imine) (PEI) on the other hand can saturate and remove surface traps to a wide extent. Implications for catalysis are discussed. [ABSTRACT FROM AUTHOR]

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels. [ABSTRACT FROM AUTHOR]