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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (pages 129-132)., Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges arise from design approach that manipulates only one level in the design stack, thus being forced to conform to constraints imposed by other levels without question. In tightly constrained environments, like embedded and mobile systems, such approaches have a hard time efficiently delivering and delivering efficiency. In this work we offer a solution that cuts through all the design stack layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software development, to relax the generality vs. efficiency/performance type tradeoffs that appear in solutions striving to achieve run-time flexibility. As a form of static polymorphism, templates typically incur very little performance overhead once the design is instantiated, thus offering the possibility to defer many design decisions until later stages when more is known about the overall system design. However, simply including templates into design flow is not sufficient to result in benefits greater than some level of code reuse. In our work we propose using templates as flexible interfaces between various levels in the design stack. As such, template parameters become the common language that designers at different levels of design hierarchy can use to succinctly express their assumptions and ideas. Thus, it is of great benefit if template parameters map directly and intuitively into models at every level. To showcase the approach w, by Ranko Radovin Sredojević., Ph.D.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (pages 59-60)., Integrated photonic links are a promising emerging technology that can relieve the interconnect bottleneck in core-to-core and core-to-memory communications of modern processors. Developing and optimizing photonic link systems requires simulation of integrated photonic devices side-by-side with electronic devices at the device, circuit, and system level. In previous efforts to simulate photonic links, the optical and the electrical signals were treated in separate simulators, which resulted in some loss of accuracy. In this thesis, a library of photonic device models is developed in Verilog-A for use in seamless simulation of opto-electronic circuits in Cadence., by Ekaterina Kononov., M. Eng.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections., Cataloged from student-submitted PDF version of thesis., Includes bibliographical references (pages 97-98)., As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low cost eye diagram reconstruction system using asynchronous undersampling technique, which solves a key problem in performance monitoring in systems where synchronous sampling is not available, such as video switches. Existing works are studied and compared to this work in performance and cost. The proposed system is designed as a system-on-chip (SOC) and contains an undersampling ADC, aliased frequency estimator and a simple reconstruction algorithm. Major building blocks are implemented and simulated in 65nm CMOS process. Extensive system level analysis and simulations demonstrate functionality and performance of the system working at 10Gb/s maximum data rate., by Shijie Zheng., M. Eng.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (pages 59-60)., Integrated photonic links are a promising emerging technology that can relieve the interconnect bottleneck in core-to-core and core-to-memory communications of modern processors. Developing and optimizing photonic link systems requires simulation of integrated photonic devices side-by-side with electronic devices at the device, circuit, and system level. In previous efforts to simulate photonic links, the optical and the electrical signals were treated in separate simulators, which resulted in some loss of accuracy. In this thesis, a library of photonic device models is developed in Verilog-A for use in seamless simulation of opto-electronic circuits in Cadence., by Ekaterina Kononov., M. Eng.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections., Cataloged from student-submitted PDF version of thesis., Includes bibliographical references (pages 97-98)., As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low cost eye diagram reconstruction system using asynchronous undersampling technique, which solves a key problem in performance monitoring in systems where synchronous sampling is not available, such as video switches. Existing works are studied and compared to this work in performance and cost. The proposed system is designed as a system-on-chip (SOC) and contains an undersampling ADC, aliased frequency estimator and a simple reconstruction algorithm. Major building blocks are implemented and simulated in 65nm CMOS process. Extensive system level analysis and simulations demonstrate functionality and performance of the system working at 10Gb/s maximum data rate., by Shijie Zheng., M. Eng.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (pages 129-132)., Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges arise from design approach that manipulates only one level in the design stack, thus being forced to conform to constraints imposed by other levels without question. In tightly constrained environments, like embedded and mobile systems, such approaches have a hard time efficiently delivering and delivering efficiency. In this work we offer a solution that cuts through all the design stack layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software development, to relax the generality vs. efficiency/performance type tradeoffs that appear in solutions striving to achieve run-time flexibility. As a form of static polymorphism, templates typically incur very little performance overhead once the design is instantiated, thus offering the possibility to defer many design decisions until later stages when more is known about the overall system design. However, simply including templates into design flow is not sufficient to result in benefits greater than some level of code reuse. In our work we propose using templates as flexible interfaces between various levels in the design stack. As such, template parameters become the common language that designers at different levels of design hierarchy can use to succinctly express their assumptions and ideas. Thus, it is of great benefit if template parameters map directly and intuitively into models at every level. To showcase the approach w, by Ranko Radovin Sredojević., Ph.D.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (pages 129-132)., Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges arise from design approach that manipulates only one level in the design stack, thus being forced to conform to constraints imposed by other levels without question. In tightly constrained environments, like embedded and mobile systems, such approaches have a hard time efficiently delivering and delivering efficiency. In this work we offer a solution that cuts through all the design stack layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software development, to relax the generality vs. efficiency/performance type tradeoffs that appear in solutions striving to achieve run-time flexibility. As a form of static polymorphism, templates typically incur very little performance overhead once the design is instantiated, thus offering the possibility to defer many design decisions until later stages when more is known about the overall system design. However, simply including templates into design flow is not sufficient to result in benefits greater than some level of code reuse. In our work we propose using templates as flexible interfaces between various levels in the design stack. As such, template parameters become the common language that designers at different levels of design hierarchy can use to succinctly express their assumptions and ideas. Thus, it is of great benefit if template parameters map directly and intuitively into models at every level. To showcase the approach w, by Ranko Radovin Sredojević., Ph.D.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013., Cataloged from PDF version of thesis., Includes bibliographical references (p. 50-53)., The demand for bandwidth in chip-to-chip communication has been increasing as the industry demands higher quantity and quality of information. Serial links provide a suitable architecture for this kind of transmission, because of speed, power and area limitations on parallel links. However, due to inter-symbol interference (ISI) and channel discontinuities, the data rate is being limited. Equalization schemes have been developed to cope with these problems. These equalizers compensate the loss of transmission mediums, equalize for reflections and extend the channel's maximum data rate. In this work, we formulate a new, nonlinear and time-variant, transmitter equalization method based on the Model Predictive Control (MPC) algorithm. MPC is a class of control algorithms in which the current control action is obtained by solving, perhaps approximately, an online open-loop optimal control problem. One important advantage of the MPC in peak-power constrained link environment is its ability to cope with hard constraints on controls and states. Knowing the state of the channel enables a very fine nonlinear equalization. We utilize this flexibility to create various MPC formulations that control the entire eyemask, receive signal dynamic range as well as the required quantization. Our MPC equalization significantly outperforms traditional transmitter techniques such as linear feed-forward and Tomlinson-Harashima equalizers, and gets very close to the optimized decision-feedback equalization at lower transmitter resolutions. We also describe the possible complexity reduction techniques that enable efficient implementation of our MPC algorithm in hardware., by Amr A. Suleiman., S.M.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010., Cataloged from PDF version of thesis., Includes bibliographical references (p. 50-51)., PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more desirable, PCIe Gen 3.0 attempts to transmit data at 8GT/s. As part of the thesis work, an existing model of a PCIe channel which connects two controller boards over a backplane, was simulated and measured under PCIe Gen 2.0 speeds (5GT/s). The resulting data from these tests were used to provide the basis for improving the model to make it function under PCIe Gen 3.0 specifications. This was achieved by exploring new receiver equalization techniques and transmitter de-emphasis and board characteristics. An integrated circuit manufacturer's model was used as the base model for PCIe Gen 2.0. This model was further developed to simulate Gen 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique., by Dilini Warnakulasuriyarachchi., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Includes bibliographical references (p. 71-72)., In this thesis, an audio CODEC receiver path has been modified by the addition of companding techniques. Companding compresses the input signal and expands the output signal according to the input power strength such that additional noise from the system is suppressed while the signal content is maintained. As the compression level is varied according to the input signal strength, transients occur at the output of the system. Sudden changes in the compression level cannot be processed instantaneously and generate transients in the output. The thesis first statically demonstrates that companding can increase the signal to noise ratio and improve the dynamic range of the audio CODEC Rx path by up to 18 dB. Further, two compensation techniques are analyzed in attempt to reduce the companding transients. The results show that transients in the output are reduced on average by 60% when using either compensation technique., by Yunjie Ma., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Includes bibliographical references (p. 71-72)., In this thesis, an audio CODEC receiver path has been modified by the addition of companding techniques. Companding compresses the input signal and expands the output signal according to the input power strength such that additional noise from the system is suppressed while the signal content is maintained. As the compression level is varied according to the input signal strength, transients occur at the output of the system. Sudden changes in the compression level cannot be processed instantaneously and generate transients in the output. The thesis first statically demonstrates that companding can increase the signal to noise ratio and improve the dynamic range of the audio CODEC Rx path by up to 18 dB. Further, two compensation techniques are analyzed in attempt to reduce the companding transients. The results show that transients in the output are reduced on average by 60% when using either compensation technique., by Yunjie Ma., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Includes bibliographical references (p. 71-72)., In this thesis, an audio CODEC receiver path has been modified by the addition of companding techniques. Companding compresses the input signal and expands the output signal according to the input power strength such that additional noise from the system is suppressed while the signal content is maintained. As the compression level is varied according to the input signal strength, transients occur at the output of the system. Sudden changes in the compression level cannot be processed instantaneously and generate transients in the output. The thesis first statically demonstrates that companding can increase the signal to noise ratio and improve the dynamic range of the audio CODEC Rx path by up to 18 dB. Further, two compensation techniques are analyzed in attempt to reduce the companding transients. The results show that transients in the output are reduced on average by 60% when using either compensation technique., by Yunjie Ma., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Includes bibliographical references (p. 71-72)., In this thesis, an audio CODEC receiver path has been modified by the addition of companding techniques. Companding compresses the input signal and expands the output signal according to the input power strength such that additional noise from the system is suppressed while the signal content is maintained. As the compression level is varied according to the input signal strength, transients occur at the output of the system. Sudden changes in the compression level cannot be processed instantaneously and generate transients in the output. The thesis first statically demonstrates that companding can increase the signal to noise ratio and improve the dynamic range of the audio CODEC Rx path by up to 18 dB. Further, two compensation techniques are analyzed in attempt to reduce the companding transients. The results show that transients in the output are reduced on average by 60% when using either compensation technique., by Yunjie Ma., M.Eng.

Includes bibliographical references (p. 75-79)., Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008., Continual increase in high-speed transfer rates is essential in today's world in order to keep up with Moor's law scaling and to meet application demands. This increase in information transfer rates is essentially limited by the bandwidth of the communication channel. Channel loss, signal crosstalk, and power integrity are the important factors affecting the bandwidth of the channel and must be fully understood when designing such high-speed links. Moreover, channel performance optimization requires system level analysis with co-design of different channel components in order to approach the maximum capacity of a channel. In this thesis, we focus on the essential aspects of high-speed channel design with an emphasis on the design of the package area. A technique for reducing discontinuities in the package is introduced, studied, and simulated on IBM package designs to obtain improved package performance. The critical Plated-Through-Hole (PTH) via region at the package and Printed Circuit Board (PCB) interface is also analyzed in a co-study to suggest design rules for overall improved system performance., by Asad Kalantarian., M.Eng.

Includes bibliographical references (p. 75-79)., Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008., Continual increase in high-speed transfer rates is essential in today's world in order to keep up with Moor's law scaling and to meet application demands. This increase in information transfer rates is essentially limited by the bandwidth of the communication channel. Channel loss, signal crosstalk, and power integrity are the important factors affecting the bandwidth of the channel and must be fully understood when designing such high-speed links. Moreover, channel performance optimization requires system level analysis with co-design of different channel components in order to approach the maximum capacity of a channel. In this thesis, we focus on the essential aspects of high-speed channel design with an emphasis on the design of the package area. A technique for reducing discontinuities in the package is introduced, studied, and simulated on IBM package designs to obtain improved package performance. The critical Plated-Through-Hole (PTH) via region at the package and Printed Circuit Board (PCB) interface is also analyzed in a co-study to suggest design rules for overall improved system performance., by Asad Kalantarian., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006., Includes bibliographical references (leaves 76-77)., Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15., by Maxine Lee., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008., Includes bibliographical references (p. 49-50)., Current techniques for characterizing the power consumption of adders rely on assuming that the inputs are completely random. However, the inputs generated by realistic applications are not random, and in fact include a great deal of structure. Input bits are more likely to remain in the same logical states from addition to addition than would be expected by chance and bits, especially the most significant bits, are very likely to be in the same state as their neighbors. Taking this data, I look at ways that it can be used to improve the design of adders. The first method I look at involves looking at how different adder architectures respond to the different characteristics of input data from the more significant and less significant bits of the adder, and trying to use these responses to create a hybrid adder. Unfortunately the differences are not sufficient for this approach to be effective. I next look at the implications of the data I collected for the optimization of Kogge- Stone adder trees, and find that in certain circumstances the use of experimentally derived activity maps rather than ones based on simple assumptions can increase adder performance by as much as 30%., by Andrew Lawrence Clough., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006., Includes bibliographical references (leaves 76-77)., Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15., by Maxine Lee., M.Eng.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008., Includes bibliographical references (p. 139-144)., This thesis explores the benefit of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a communication system with noise and intersymbol interference (ISI), this work identifies three operating regimes based on the underlying dominant error mechanisms. The resulting framework is used to identify the conditions under which standard error control codes perform optimally, incur an impractically large overhead, or provide the optimal performance in the form of a single parity check code. For the regime where the standard error control codes are impractical, this thesis introduces low-complexity block codes, termed pattern-eliminating codes (PEC), which achieve a potentially large performance improvement over channels with residual ISI. The codes are systematic, require no decoding and allow for simple encoding. They can also be additionally endowed with a (0, n - 1) run-length-limiting property. The simulation results show that the simplest PEC can provide error-rate reductions of several orders of magnitude, even with rate penalty taken into account. It is also shown that channel conditioning, such as equalization, can have a large effect on the code performance and potentially large gains can be derived from optimizing the equalizer jointly with a pattern-eliminating code. Although the performance of a pattern-eliminating code is given by a closed-form expression, the channel memory and the low error rates of interest render accurate simulation of standard error-correcting codes impractical. This work proposes performance estimation techniques for coded high-speed links, based on the underlying regimes of operation., (cont)It also introduces an efficient algorithm for computing accurate marginal probability distributions of signals in a coded high-speed link., by Natasa Blitvic., S.M.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008., Includes bibliographical references (p. 49-50)., Current techniques for characterizing the power consumption of adders rely on assuming that the inputs are completely random. However, the inputs generated by realistic applications are not random, and in fact include a great deal of structure. Input bits are more likely to remain in the same logical states from addition to addition than would be expected by chance and bits, especially the most significant bits, are very likely to be in the same state as their neighbors. Taking this data, I look at ways that it can be used to improve the design of adders. The first method I look at involves looking at how different adder architectures respond to the different characteristics of input data from the more significant and less significant bits of the adder, and trying to use these responses to create a hybrid adder. Unfortunately the differences are not sufficient for this approach to be effective. I next look at the implications of the data I collected for the optimization of Kogge- Stone adder trees, and find that in certain circumstances the use of experimentally derived activity maps rather than ones based on simple assumptions can increase adder performance by as much as 30%., by Andrew Lawrence Clough., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006., Includes bibliographical references (leaves 76-77)., Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15., by Maxine Lee., M.Eng.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008., Includes bibliographical references (p. 139-144)., This thesis explores the benefit of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a communication system with noise and intersymbol interference (ISI), this work identifies three operating regimes based on the underlying dominant error mechanisms. The resulting framework is used to identify the conditions under which standard error control codes perform optimally, incur an impractically large overhead, or provide the optimal performance in the form of a single parity check code. For the regime where the standard error control codes are impractical, this thesis introduces low-complexity block codes, termed pattern-eliminating codes (PEC), which achieve a potentially large performance improvement over channels with residual ISI. The codes are systematic, require no decoding and allow for simple encoding. They can also be additionally endowed with a (0, n - 1) run-length-limiting property. The simulation results show that the simplest PEC can provide error-rate reductions of several orders of magnitude, even with rate penalty taken into account. It is also shown that channel conditioning, such as equalization, can have a large effect on the code performance and potentially large gains can be derived from optimizing the equalizer jointly with a pattern-eliminating code. Although the performance of a pattern-eliminating code is given by a closed-form expression, the channel memory and the low error rates of interest render accurate simulation of standard error-correcting codes impractical. This work proposes performance estimation techniques for coded high-speed links, based on the underlying regimes of operation., (cont)It also introduces an efficient algorithm for computing accurate marginal probability distributions of signals in a coded high-speed link., by Natasa Blitvic., S.M.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006., Includes bibliographical references (leaves 76-77)., Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15., by Maxine Lee., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006., Includes bibliographical references (leaves 76-77)., Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15., by Maxine Lee., M.Eng.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008., Includes bibliographical references (p. 49-50)., Current techniques for characterizing the power consumption of adders rely on assuming that the inputs are completely random. However, the inputs generated by realistic applications are not random, and in fact include a great deal of structure. Input bits are more likely to remain in the same logical states from addition to addition than would be expected by chance and bits, especially the most significant bits, are very likely to be in the same state as their neighbors. Taking this data, I look at ways that it can be used to improve the design of adders. The first method I look at involves looking at how different adder architectures respond to the different characteristics of input data from the more significant and less significant bits of the adder, and trying to use these responses to create a hybrid adder. Unfortunately the differences are not sufficient for this approach to be effective. I next look at the implications of the data I collected for the optimization of Kogge- Stone adder trees, and find that in certain circumstances the use of experimentally derived activity maps rather than ones based on simple assumptions can increase adder performance by as much as 30%., by Andrew Lawrence Clough., M.Eng.