Channel-and-circuits aware, energy-efficient coding for high speed links

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (leaves 76-77).
Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error rate lower than 10-15. While applicable to data rates up to 10 Gb/s on most links, this approach does not scale well to higher data rates or better energy-efficiency. The work described in the thesis shows that it may be possible to use coding techniques to share the burden of combating errors, while increasing the throughput of the link or improving its energy-efficiency. Since codes here attempt to alleviate the impact of partially correlated sources of error (like reflections interference, crosstalk and jitter), an experimental setup was created for characterization of link channel properties and performance gains from different codes. Four codes, specifically Hamming, BCH, Fire, and SEC-DED codes, are implemented and analyzed with various configurations (i.e. different blocksizes, data rates, and detection or correction). Most significantly, it is discovered that detection and retransmission of even the simple codes implemented in this project may be able to maintain a bit error rate of 10-15.
by Maxine Lee.
M.Eng.