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The proposal and processing aspects of the prove-of-concept InGaN/GaN/AlGaN/GaN metal-oxide-semiconductor (MOS) high-electron mobility transistor with etched access regions are addressed. Full strain and decent quality of the epitaxial system comprising 4 nm In0.16Ga0.84N/3 nm GaN/5 nm Al0.27Ga0.73N are observed using a high-resolution transmission-electron microscopy and by deformation profile extractions. Large negative polarization charge in the MOS gate stack provides the HEMT normally-off operation, while free electrons are populated at access regions after etching. Consecutive passivation by 10 nm Al2O3 together with annealing at 300 °C improved the Al2O3/semiconductor interface, with the threshold voltage (V T ) reaching 1 V. Improvements of the present concept in comparison to the previous one with a gate recess were proved by showing the decreased drain leakage current and increased breakdown voltage.

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm–14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

We investigate the properties of high-k dielectric insulators on GaN. 22 nm thick ZrO2 is deposited on N- or Ga-polarity GaN. Al/ZrO2/GaN metal–oxide–semiconductor and reference Au/Ni/GaN Schottky contact structures are characterized using current–voltage and capacitance–voltage methods. If compared with Schottky contacts, metal–oxide–semiconductor structures show leakage current substantially reduced for the N-polarity GaN while comparable values were obtained for the Ga-polarity GaN. The oxide relative permittivity is found to be in the range of 20–30. Light-assisted capacitance–voltage method shows density of interface states Dit ~ 1 × 1012 cm−2 eV−1 for Ga-polarity and ~2 × 1012 cm−2 eV−1 for N-polarity GaN/ZrO2. Finally, we prepared AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistor proving minimal transconductance deterioration and small threshold voltage shift. It is suggested that ZrO2 deposition optimization may further reduce the leakage current.

The replacement of the AlGaN barrier layer of the AlGaN/GaN high electron mobility transistors (HEMTs) with InAlN of various In molar fractions is suggested. Internal polarization fields in the InAlN/(In)GaN quantum well are described using analytical formulae. InAlN/(In)GaN HEMTs quantum well free electron densities, transistor open channel drain currents and threshold voltages are calculated for different In molar fractions considering the maximal acceptable strain. It is suggested that 0.08 ≤ x ≤ 0.27 for a 15 nm thick InxAl1−xN barrier or 0 ≤ y ≤ 0.18 for a 5–10 nm thick InyGa1−yN channel can be applied for strain without layer relaxation while the quantum well free electron densities up to 4.6 × 1017 m−2 and the transistor open channel drain currents up to 4.5 A mm−1 can be expected.

The design and performance of a thermally-actuated GaAs cantilever beam are presented. To actuate the cantilever beam an integrated GaAs MESFET heater was used. A comprehensive cantilever thermal actuation performance is analysed by experiment and simulation. The thermally-actuated GaAs cantilever shows excellent linearity and a high electro-mechanical conversion efficiency (?E = 0.802??m?mW-1). The method of two-dimensional numerical modelling and simulation is proposed to study its thermal and thermo-mechanical properties. The measured and simulated thermo-mechanical and electro-mechanical conversion characteristics are compared, indicating the viability of the simulation method used for further micromechanical analysis.

We describe the technology and performance of integrated enhancement/depletion (E/D)-mode n(++) GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate structure. An identical starting epi-structure was used for both types of devices without the additional need for a contacts regrowth. The n(++) GaN cap layer was etched away in the gate trenches of the E-mode HEMT while it was left intact for the D-mode HEMT. The plasma etching process was shown to be highly selective between the cap and the InAlN barrier and also to polish the InAlN surface. However, different GaN etching initiation times inside and outside the mesa region were obtained. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Feasibility of the approach for future fast GaN-based mixed-signal electronic circuits was shown by obtaining alternative HEMT threshold voltage values of +0.8 V and -2.6 V, invariant maximal output current of similar to 0.35 A mm(-1) despite large source-to-drain distances and by demonstrating a functional logic invertor.

The formation of Schottky contacts on methane/hydrogen reactive-ion-etched (RIE) n+In0.52Al0.48As surfaces has been investigated for the first time. Two metallization systems (Ti/W/Au and Pt/Au) were examined. The ion etching-induced damage in the InAlAs surface layer was evaluated by means of I-V and C-V characterization. Rapid thermal annealing (RTA) at several temperatures was applied for damage removal. Dry-etched Schottky contacts were compared with wet-etched ones. Using the optimized condition of RTA, parameters achieved on RIE-based Schottky contacts were in agreement with theoretical predictions and comparable with thermally processed wet-based ones. The role of the thermal treatment in the final determination of metal-semiconductor interface and contact properties is discussed in detail.

The influence of annealing on properties of Pt Schottky contacts deposited on the electron cyclotron resonance plasma etched surface of an AlGaN/GaN heterostructure has been investigated. It is found that rapid thermal annealing (450 °C and 40 s in nitrogen gas), performed after metal deposition, allows for the preparation of Schottky contacts with similar or better properties than those obtained on a non-etched surface. This procedure is suitable for the realization of recessed high-quality Schottky contacts of AlGaN/GaN HEMTs.

The PHOTOFET method is applied to submicrometre MESFETS processed on ion-implanted Cr-doped substrates. It is demonstrated that the magnitude of the photoconductivity both under extrinsic and intrinsic illumination is determined by the substrate leakage current, which is a function of the device drain bias. A semiempirical modeling of the dependence of the photoconductivity on the device bias gives a power-law relation between the leakage current and the drain bias.

We propose N-polar normally-off InN-channel high-electron mobility transistors (HEMTs). A calculated energy band diagram shows full depletion of a quantum well channel provided by a negative polarization charge at an InN-channel/GaN-cap junction. For a 100 nm long gate-length HEMT with a 3 nm thick InN channel, 0.4 nm GaN cap and 4 nm thick HfO2/ZrO2 insulator we calculate a threshold voltage VT = 0.5 V and a transconductance of 3 S mm−1. Selective plasma etching of the GaN cap over the InN channel may facilitate monolithic integration of normally-off and -on InN channel HEMTs in a new generation of extremely fast digital circuits.

We experimentally prove the viability of the concept of the double-heterostructure quantum well InAlN/GaN high-electron-mobility transistor (HEMT) for the device higher robustness and reliability. In the single quantum well InAlN/GaN HEMTs, the intrinsic channel resistance increases by 300% after 1 h off-state stress; much less degradation is observed in the double-heterostructure device with an AlGaN back barrier. Physics-based device simulation proves that the back barrier blocks the rate of carrier injection into the device buffer. However, whatever the quantum well design is, the energy of the injected electrons in the buffer of InAlN/GaN-based HEMTs is higher than that in the buffer of AlGaN/GaN HEMTs. This energy may be sufficient for releasing hydrogen from GaN point defects.

Using a coupled Schrodinger–Poisson equation solver, we propose an N-polarity InN-channel quantum well high-electron-mobility transistors. The structure comprises from the bottom, a relaxed InAlN buffer with Al mole fraction between 0.1 and 0.3, GaN spacer with thickness less than 1 nm, 5 nm strained InN, and 5 nm ZrO2 or HfO2 to insulate a gate. Depending on the Al mole fraction, calculations indicate highly confined electrons in the channel with a two-dimensional density ranging from 1.6×1013 to 3.5×1013 cm-2. The polarity of the structure provides a possibility to grow InN as the last III-N layer with a relatively low polarization charge at the surface.

We investigate Al2O3- and ZrO2/InAlN/GaN metal-oxide-semiconductor heterostructures (MOS-H) using capacitance-time transients in the temperature range of 25-300 degrees C. A deep-level transient spectroscopy based analysis revealed the maximum interface state density distributions D-it(E) up to 3 x 10(13) and 1 X 10(13) eV(-1) cm(-2) for the Al2O3/InAlN and ZrO2/InAlN interface, respectively. The integral densities of interface states correlate well with the trapping-related gate-lag effect in corresponding InAlN/GaN MOS high electron mobility transistors (HEMTs). This explains the strongly reduced lag effect in ZrO2 MOS HEMTs. We assume hole trapping at oxide/InAlN interface to be a dominant effect responsible for the gate-lag effect in InAlN/GaN MOS HEMTs. (C) 2009 The Japan Society of Applied Physics 10.1143/JJAP.48.090201