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Room temperature near-infrared electroluminescence (EL) from Si/CaF2 quantum cascade laser structures has been demonstrated. The structure was equipped with 25 periods of the active region comprised of Si/CaF2 multi quantum-wells and single-mode waveguide grown by molecular beam epitaxy-based technique on the silicon-on-insulator (SOI) substrate. EL spectra with multiple peaks around the near-infrared region were obtained at room temperature and the EL intensity response with injection current clearly confirmed the EL emission was originated from the current injection. Moreover, it was found that EL peak shift by changing applied bias was reasonably explained by energy shift due to the electric field applied to the Si quantum-well of the active region.

We investigated the effects of the post-oxidation annealing in H2O (wet-POA) with various conditions after dry oxidation for p-type 4H-SiC (0001) metal-oxide-semiconductor (MOS) capacitors and 4H-SiC (0001) p-channel MOS field effect transistors (PMOSFETs). Interface state density, fixed charge density, and slow trap density in near-interface oxide were reduced by the wet-POA with additional growth of only < 1 nm oxide at the interface. With those POAs the improved PMOSFET performance was also demonstrated. The degradation of flatband voltage (VFB) stability, which has been regarded as one of the serious drawbacks of wet oxidation of SiC, was efficiently suppressed by a careful selection of the wet-POA conditions with low O2 partial pressure at high temperature. Even though the reason why the VFB stability is so sensitive to the wet-POA condition is not clarified yet, these results give us a guideline to design an appropriate conditions of wet-POA for SiC PMOSFETs.

A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub-μm as well as 10 μm width copper through-silicon-vias (Cu-TSVs). Micro-structural data revealed that both sub-μm and 10 μm width TSVs with AR ranging from 12 to 17 were completely filled with Cu by using EL-Ni as a seed layer. Further, both scanning electron microscope and energy dispersive X-ray analyzes data confirms the conformal formation of EL-Ni all through TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method appears to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future three-dimensional integration and packaging applications.

In the context of sensing and characterizing single proteins with synthetic nanopores, lipid bilayer coatings provide at least four benefits: first, they minimize unwanted protein adhesion to the pore walls by exposing a zwitterionic, fluid surface. Second, they can slow down protein translocation and rotation by the opportunity to tether proteins with a lipid anchor to the fluid bilayer coating. Third, they provide the possibility to impart analyte specificity by including lipid anchors with a specific receptor or ligand in the coating. Fourth, they offer a method for tuning nanopore diameters by choice of the length of the lipid’s acyl chains. The work presented here compares four properties of various lipid compositions with regard to their suitability as nanopore coatings for protein sensing experiments: (1) electrical noise during current recordings through solid-state nanopores before and after lipid coating, (2) long-term stability of the recorded current baseline and, by inference, of the coating, (3) viscosity of the coating as quantified by the lateral diffusion coefficient of lipids in the coating, and (4) the success rate of generating a suitable coating for quantitative nanopore-based resistive pulse recordings. We surveyed lipid coatings prepared from bolaamphiphilic, monolayer-forming lipids inspired by extremophile archaea and compared them to typical bilayer-forming phosphatidylcholine lipids containing various fractions of curvature-inducing lipids or cholesterol. We found that coatings from archaea-inspired lipids provide several advantages compared to conventional phospholipids; the stable, low noise baseline qualities and high viscosity make these membranes especially suitable for analysis that estimates physical protein parameters such as the net charge of proteins as they enable translocation events with sufficiently long duration to time-resolve dwell time distributions completely. The work presented here reveals that the ease or difficulty of coating a nanopore with lipid membranes did not depend significantly on the composition of the lipid mixture, but rather on the geometry and surface chemistry of the nanopore in the solid state substrate. In particular, annealing substrates containing the nanopore increased the success rate of generating stable lipid coatings.

We report the experimental results of X-ray computed tomography (X-CT) of directed self-assembly (DSA) formed metal-containing nanocylinders with a width in the range of 25–30 nm. We compare the X-CT results for DSA formed metal nanowires inside deep Si trenches with those of conventional morphological characterization techniques such as scanning electron microscopy (SEM) and transmission electron microscopy (TEM). It is found that X-CT is more reliable than SEM and TEM, especially when analyzing the 3D nanometer-sized structures embedded in the organic matrix.

We have grown single crystals of WTe2 by a self-flux method and evaluated the quality of the crystals. A Hall bar-type device was fabricated from an as-exfoliated film on a Si substrate and longitudinal resistance Rxx was measured. Rxx increased with an applied perpendicular magnetic field without saturation and an extremely large magnetoresistance as high as 376,059 % was observed at 8.27 T and 1.7 K.

A new interposer with an optical interconnection called optical interposer has been proposed for a high-performance parallel processor system. The optical interposer is composed of polynorbornene (PNB) optical waveguides with 45° micromirrors and a Si substrate having chip-sized through-Si holes of 150 µm depth. The polymeric waveguides are formed on the Si substrate before forming the through-Si holes by deep reactive ion etching (DRIE). Vertical-cavity surface-emitting laser diode (VCSEL) and photodiode (PD) chips are placed onto the photolithographically defined hole patterns that are 15 µm larger than the size of the chips. In addition, the chips can be precisely aligned and recessed into the holes by passive alignment of self-assembly driven by the surface tension of a lead-free solder. We can fabricate the low-loss optical interposer with an insertion loss of below 0.2 dB measured at the waveguide length of 5 cm and a coupling loss of 0.5 dB measured with a 45° micromirror.

Tungsten through-silicon via (W-TSV) technology is investigated for the fabrication of three-dimensional (3D) LSI chips having low-resistive TSVs with a width less than 3 µm. In our 3D integration technology, completed two-dimensional (2D) LSI chips including metal–oxide–semiconductor field-effect transistors (MOSFETs) and metal wirings are vertically stacked through a number of short vertical interconnections called TSV with lengths ranging from several microns to several tens of microns. The W-TSV technology is mainly divided into three low-temperature processes: deep-trench etching, dielectric layer formation, and filling with a conductive material. We successfully formed deep Si trenches through a 6-µm-thick SiO2 dielectric layer by the modified Bosch process. The depth of the resulting Si trenches with a dielectric layer is approximately 40 µm. A SiO2 layer was formed at the bottom and on the sidewall of the Si trenches by sub-atmospheric chemical vapor deposition (SACVD) method using tetraethylorthosilicate (TEOS) and O3. In addition, we succeeded in uniformly depositing a conformal W metal layer by time-modulated W-CVD method at 300 °C.

We have proposed a new retinal prosthesis system consisting of a three-dimensionally (3-D) stacked retinal prosthesis chip, a flexible cable with an electrode array stimulus, and a power supply system for the retinal prosthesis chip. Electromagnetic induction with a primary coil and a secondary coil was employed as the power supply system. The power was transmitted to the retinal prosthesis chip through an RF/DC voltage conversion chip that converted AC voltage into DC voltage. The 3-D stacked retinal prosthesis chip operates with a DC supply voltage of 3.3 V, and the secondary coil requires a transmitted voltage that is 1 V higher than the DC supply voltage. In order to receive a sufficient supply voltage, several parameters such as external supply voltage and transmission frequency were optimized. A peak RF voltage of 4.5 V was obtained when we employed a primary coil with 50 turns, a secondary coil with 20 turns, an external supply voltage of 4.1 V, and a frequency of 3 MHz. We also successfully fabricated Schottky barrier diodes to rectify the RF voltage received by the secondary coil. The fabricated Schottky barrier diodes have a high breakdown voltage of 4.6 V, which is sufficient for our 3-D stacked retinal prosthesis chip.

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

We study the electronic structures of MnX (X=As, Sb, and Bi) in a ferromagnetic phase based on the density functional theory within the local spin density approximation using a fully relativistic full-potential linear-combination-of-atomic-orbitals method. In particular, we focus on the effects of spin–orbit coupling. To this end, we compare the results of the fully relativistic calculations with those of the scalar relativistic calculations. It is found that the splitting of energy bands caused by spin–orbit coupling is on the order of 0.05, 0.15, and 0.35 eV for MnAs, MnSb, and MnBi, respectively. Furthermore, we compare the results of this study with those of other theoretical studies to examine the reliability of our results.

An optical interconnection with a new optically transparent polymer called polynorbornene (PNB) was investigated for short-distance and high-speed data transmission on printed circuit boards (PCBs). PNB waveguides were formed by simple photoirradiation followed by heating without development and reactive ion etching (RIE) processes. The PNB waveguides exhibit a high-heat resistance of more than 270 °C and an extremely low optical loss of 0.029 dB/cm at 830 nm. We successfully integrated PNB waveguides into a multilayer PCB, which we call a optical/electrical printed circuit board (O/E-PCB), and confirmed a basic data transmission rate of 10 Gbps.

We describe a new writing scheme with a selective word line bootstrap for spin-transfer magnetoresistive random access memory (MRAM). Applying spin-transfer switching to MRAM, its writing power consumption decreases and its memory cell area is also reduced. However, during write operation, the required bit line cramp voltage for stored data switching depends on the value of stored data, magnetic tunnel junction (MTJ) characteristics, and switching current direction. Therefore, the bit line voltage must be optimized to minimize the power consumption. With the proposed scheme, word line voltage is varied according to the value of writing data in order to decrease the threshold bit line voltage. Furthermore, the spin-transfer MRAM resistance model with reading and writing operations was successfully implemented for the circuit simulation. From the simulation results, it was found that writing threshold bit line bias during writing operation can decrease from 17 to 28% with the proposed selective bootstrap. Also, more than 25% of the cell transistor gate width can be decreased. This result shows that the proposed writing scheme is effective in reducing power consumption, and can also reduce the MRAM cell area.

A retinal prosthesis system with a three-dimensionally (3D) stacked LSI chip has been proposed. We fabricated a new implantable stimulus electrode array deposited with Platinum-black (Pt-b) on a polyimide-based flexible printed circuit (FPC) for the electrical stimulation of the retinal cells. Impedance measurement of the Pt-b electrode–electrolyte interface in a saline solution was performed and the Pt-b electrode realized a very low impedance. The power consumption at the electrode array when retinal cells were stimulated by a stimulus current was evaluated. The power consumption of the Pt-b stimulus electrode array was 91% lower than that of a previously fabricated Al stimulus electrode array due to a convexo-concave surface. In the cytotoxicity test (CT), we confirmed that Pt implantation induced no cellular degeneration of the rat retina. In the animal experiments, electrically evoked potential (EEP) was successfully recorded using Japanese white rabbits. These results indicate that electrical stimulation using the Pt-b stimulus electrode array can restore visual sensation.

A new magnetic nanodot (MND) memory with FePt nanodots was proposed. The FePt nanodots dispersed in SiO2 insulating film was successfully fabricated by self-assembled nanodot deposition (SAND). The size of the FePt nanodot can be controlled by SAND with a different target area ratio of the FePt pellets area in the SiO2 target. Thermal annealing converts the magnetic properties of the FePt nanodots from antiferromagnetic into high coercivity ferromagnetic without thermal agglomeration. An L10 face-centered tetragonal (fct) FePt MND film was successfully formed which acted as a charge retention layer. Furthermore, the fundamental characteristics of the MND memory were investigated using magnetic metal oxide semiconductor (MOS) capacitor devices.

We have developed a novel AFM (atomic force microscope) measurement technique which can examine side-walls of fine patterns etched into wafers. This technique uses a sharpen tip tilted at an angle in combination with a "step-in" mode operation, and is thus referred as "tilt-step-in" mode. This method allows one to measure side wall shape including under cut and line edge roughness (LER).

Since FY 2004, a four-year Japanese national project has been ongoing to develop an HTS-SMES as a sub-program of the Development of Superconducting Power Network Control Technology. The purpose of this project is to confirm the performance of a high energy density SMES coil with Bi-2212 cables. This coil system is composed of an NbTi outer coil and a Bi-2212 inner coil, consisting of 16 double pancakes. A Bi2212 cable of 140 m length is used for the double-pancake windings, and reinforcing materials are co-wound with the cable. A winding inner diameter of 360 mm was set according to the bending tolerance of the cable. The magnet is to be cooled at 4.2 K by liquid helium in order to obtain high overall current density. In the first year of this project, a conceptual design and various experiments for HTS magnet were carried out. This paper describes the test results of the HTS experimental coil that was developed to evaluate the electrical and thermal characteristics of an HTS. It is important to minimize deterioration and damage to the cable, because such defects cause fatal impact to the coil. Consequentially, high accuracy measurement of V-I characteristics up to10−8 V/cm range was performed in this experiment.

Three-dimensional (3D) integration is the most promising technology to improve IC performance by stacking some active device layers and connecting them using vertical interconnections. In this paper, in order to quantitatively evaluate the benefits of 3D IC, wire length distributions in 3D ICs are derived by adapting the simulated quenching algorithm for 3D placement and routing of specific benchmark circuits. By evaluating the wire length distribution, we can confirm that the total wire length is reduced by 26.0 and 41.3% with three and five active layers, respectively. Similarly, 38.1 and 52.0% reduction in the longest wire length with three and five active layers can be achieved.

A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In–Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 µm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.

For high-speed and low-power performance, ultrathin body (UTB) silicon on insulator (SOI) metal oxide semiconductor field-effect semiconductors (MOSFETs) with an elevated source/drain (ESD) have been investigated using selectively epitaxial growth (SEG) technology. In this work, we found that the morphology of a SEG layer on an ultrathin Si film and the crystallinity of the top Si film are strongly dependent on ion implantation damage. The morphology and surface roughness of SEG layers were investigated by field emission scanning electron microscopy (FE-SEM) and the crystallinities of the top silicon films with and without ion implantation were characterized by atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS), respectively. Furthermore, to suppress ion implantation damage, a SEG layer was formed before ion implantation for source drain extension (SDE) formation by the sacrificial sidewall spacer method. As results, UTB SOI-MOSFETs with a flat ESD were successfully fabricated by the proposed method.

Magnetoresistive random access memory (MRAM) has recently attracted considerable attention due to its non-volatility and high programming speed. A high Tunnel magnetoresistance (TMR) ratio is a key factor of MRAM. However, a conventional MRAM using aluminum oxide as insulator film shows a low TMR ratio of several tens of percents. MgO tunneling insulator is one of the candidates for achieving a high TMR ratio. In this study, we fabricated and evaluated Magnetic tunnel junctions (MTJs) with MgO tunneling barrier on a clad Cu word line.

A new multichip shared memory module with optical interconnection for a parallel-processor system was introduced. The new shared memory module mainly consists of shared memory units optically connected to one another through polyimide waveguides and electrically connected to processor elements. We designed and fabricated a static random access memory (SRAM) test chip which has an optical/electrical (O/E) receiver circuit and electrical/optical (E/O) transmitter circuit for optical data transfer. A vertical-cavity surface-emitting laser diode (VCSEL) was integrated onto an LSI chip by the beam-lead bonding technique. Optical data transfer was achieved using polyimide optical waveguides with Al micromirrors formed on a Si substrate called an optical plate, and the optical writing and electrical reading operation in the SRAM test chip was successfully demonstrated.

Deep-Si-trench etching was investigated to establish chip-to-chip three-dimensional (3D) integration technology where completed two-dimensional (2D) LSI chips fabricated using standard complementary metal oxide semiconductor (CMOS) technology can be vertically stacked through a number of vertical interconnections formed in the 2D LSI chips. The formation of deep Si trenches through dielectric layers is a key process in chip-to-chip 3D integration technology. In this process, trench profile is an important factor to achieve the complete filling of the resulting deep Si trenches with conductive materials. We have successfully obtained deep Si trenches with a depth of 28 µm through a 7-µm-thick SiO2 layer by inductively coupled plasma (ICP) etching using a time-modulated bias. The desirable high-aspect-ratio Si trenches with a forward tapered shape, a 3.0 µm top width and a 2.4 µm bottom width were also formed in a Si test chip glued on a Si wafer supporting material by the Bosch process.

We have proposed a novel multilayer stacked retinal prosthesis chip based on three-dimensional integration technology. Implantable stimulus electrode arrays in polyimide flexible cables were fabricated for the electrical stimulation of the retina. To evaluate optimal retinal stimulus current, electrically evoked potential (EEP) was recorded in animal experiments using Japanese white rabbits. The EEP waveform was compared with visually evoked potential (VEP) waveform. The amplitude of the recorded EEP increased with stimulus current. The EEP waveform shows a similar behavior to the VEP waveform, indicating that the electrical stimulation of the retina can be exploited for the blind to perceive incident light to the retina.

A novel flash memory which has FePt magnetic floating gate was proposed. An FePt magnetic floating gate with a high coercivity was successfully fabricated by DC magnetron sputtering with rapid thermal annealing. As for magnetic properties, the switching magnetic fields of 21 Oe for the NiFe film and 1600 Oe for the FePt film were employed for the control gate and the floating gate materials, respectively. The fundamental characteristics of the magnetic flash memory were confirmed using magnetic metal oxide semiconductor (MOS) capacitor devices and magnetic tunneling diode (MTD) devices.

We proposed a silicon-on-low k insulator (SOLK) metal oxide semiconductor field effect transistor (MOSFET) with a metal back gate for high-speed and ultralow power devices. In this work, Benzocyclobutene (BCB) and tetramethyl ammonium hydroxide (TMAH) were employed to fabricate SOLK Devices without damaging the transistor channels. We successfully fabricated the proposed submicron fully depleted (FD) SOLK MOSFETs with a metal back gate. The process technologies and electrical properties of SOLK MOSFETs were introduced in detail. Furthermore, threshold voltage shift was obtained at 55 mV/V using a NMOSFET and at 35 mV/V using a PMOSFET and drain current characteristics are enhanced by the back gate bias.

In this paper, we describe a new magnetoresistive random access memory (MRAM) sensing scheme with a body-biased preamplifier for low-power and high-sensitivity operation. The proposed new MRAM sense amplifier consists of a current sense preamplifier with a body biasing differential pair of a common-gate amplifier and a voltage sense amplifier. The preamplifier controls bitline voltage appropriately and amplifies the difference in bitline current as current-mode sense amplifier. The new sense amplifier enhances sensitivity, and the body-biased preamplifier enables low-voltage operation. To evaluate the proposed circuit, the modeling of magnetic tunnel junction (MTJ) resistance characteristics was performed with a VHDL-AMS description, and the proposed circuit was simulated with a mixed signal circuit simulator. From the simulation result, it is confirmed that the proposed sensing scheme results in a 1.57 times faster access time than a conventional scheme, and that the power of the sense amplifier is lower than that of the conventional amplifier at the same speed.

The electronic structure of YbFe4Sb12, which shows heavy-fermion or mixed-valence behaviour, are studied by high-resolution photoemission spectroscopy. The observed Yb2+ signal is composed of two spin–orbit doublets which might be interpreted as bulk and surface contributions. The relationship between the energy positions of the two doublets is anomalous compared to those of the conventional mixed-valence Yb compounds.

Sintered degenerate n-type PbTe samples with a grain size down to about 0.2 ?m were prepared and their thermoelectric properties subsequently measured. Accordingly, the effects of grain size on thermoelectric properties were investigated. For samples with a grain size above ?0.5 ?m, the Seebeck coefficient and thermoelectric figure-of-merit increased with decreasing grain size. In particular, the room-temperature figure-of-merit reached a maximum value of ?4?10-4 K-1, which is about twice as large as the value of a large-grain-size sample with the same carrier concentration reported in the literature. For samples with a grain size below ?0.5 ?m, with decreasing grain size, the Seebeck coefficient increased but the figure-of-merit did not increase because of a substantial decrease in electrical conductivity. The increase in the Seebeck coefficient with decreasing grain size was probably caused by the potential barrier scattering at grain boundaries. On the other hand, the decrease in electrical conductivity is explained mainly by the porosity effect. Thus, we consider that if a sintered PbTe sample with a smaller grain size and a lower porosity is prepared, a larger improvement in the figure-of-merit due to the potential barrier scattering can be obtained.

Heavy-ion radiotherapy has a high curative effect in cancer treatment and also can reduce the burden on patients. These advantages have been generally recognized. Furthermore, a rotating gantry can irradiate a tumor with ions from any direction without changing the position of the patient. This can reduce the physical dose on normal cells, and is thus commonly used in proton radiotherapy. However, because of the high magnetic rigidity of carbon ions, the weight of the rotating gantry for heavy-ion therapy is about three-times heavier than those used for proton cancer therapy, according to our estimation. To overcome this issue, we developed a small and lightweight rotating gantry in collaboration with the National Institute of Radiological Sciences (NIRS). The compact rotating gantry was composed of ten low-temperature superconducting (LTS) magnets that were designed from the viewpoint of beam optics. These LTS magnets have a surface-winding coil-structure and provide both dipole and quadrupole fields. The maximum dipole and quadrupole magnetic field of the magnets were 2.88 T and 9.3 T/m, respectively. The rotating gantry was installed at NIRS, and beam commissioning is in progress to achieve the required beam quality. In the three years since 2013, in a project supported by the Ministry of Economy, Trade and Industry (METI) and the Japan Agency for Medical Research and Development (AMED), we have been developing high-temperature superconducting (HTS) magnets with the aim of a further size reduction of the rotating gantry. To develop fundamental technologies for designing and fabricating HTS magnets, a model magnet was manufactured. The model magnet was composed of 24 saddle-shaped HTS coils and generated a magnetic field of 1.2 T. In the presentation, recent progress in this research will be reported.

Investigation of fatigue strength of extruded AZ31 magnesium alloy was performed by ultrasonic fatigue tests (test frequency about 19500Hz) and taken to compare with conventional tension-compression fatigue tests (20Hz). The fatigue life under ultrasonic loading exhibits longer than the conventional one. Effects of ultrasonic frequency on the S-N curve, crack initiation and growth behaviour of AZ31 alloy is discussed. This work would be useful for improving the ultrasonic fatigue test method to observe the fatigue behaviour in very high cycle regime.

Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 °C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 °C, and nearly vanished after annealing at 400 °C. The immense importance of 400 °C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 °C has tremendous potential for implementation in cost-effective via-last 3D integration.

The relative density of chlorine molecular ions (Cl + 2 ) was measured in both continuous-wave (cw) and time-modulated inductively coupled chlorine plasma by the laser-induced fluorescence technique. The Cl + 2 density was modulated by 30% under a modulation frequency of 100 kHz. At high rf power, the Cl + 2 density in the time-modulated plasma was found to be higher than that in the cw plasma. In addition, the Doppler profile of Cl + 2 was measured to evaluate Cl + 2 temperature.