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New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration
- Source :
- Japanese Journal of Applied Physics. 45:3030-3035
- Publication Year :
- 2006
- Publisher :
- IOP Publishing, 2006.
-
Abstract
- A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In–Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 µm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.
- Subjects :
- Interconnection
Fabrication
Materials science
Physics and Astronomy (miscellaneous)
business.industry
Wafer bonding
General Engineering
General Physics and Astronomy
Hardware_PERFORMANCEANDRELIABILITY
engineering.material
Chip
Polycrystalline silicon
Stack (abstract data type)
Chemical-mechanical planarization
Hardware_INTEGRATEDCIRCUITS
engineering
Optoelectronics
business
Flip chip
Subjects
Details
- ISSN :
- 13474065 and 00214922
- Volume :
- 45
- Database :
- OpenAIRE
- Journal :
- Japanese Journal of Applied Physics
- Accession number :
- edsair.doi...........be5770b380bdb6ed53b2ec88fe0703f1