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Your search keyword '"Mario C. Vélez-Gallego"' showing total 4 results
Start Over Author "Mario C. Vélez-Gallego" Publisher institute of industrial engineers ( iie )
4 results on '"Mario C. Vélez-Gallego"'

1. Minimizing Makespan in a No-Wait Flow Shop With Batch Processing Machines

Author

Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Muthuswamy, Shanthi, Mario C. Vélez-Gallego, Maya, Jairo, Rojas-Santiago, Miguel, Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Muthuswamy, Shanthi, Mario C. Vélez-Gallego, Maya, Jairo, Rojas-Santiago, and Miguel

Abstract

Given a set of jobs and two batch processing machines (BPMs) arranged in a flow shop environment, the objective is to batch the jobs and sequence the batches such that the makespan is minimized.

Published
2021

2. Minimizing Makespan in a No-Wait Flow Shop With Batch Processing Machines

Author

Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Muthuswamy, Shanthi, Mario C. Vélez-Gallego, Maya, Jairo, Rojas-Santiago, Miguel, Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Muthuswamy, Shanthi, Mario C. Vélez-Gallego, Maya, Jairo, Rojas-Santiago, and Miguel

Abstract

Given a set of jobs and two batch processing machines (BPMs) arranged in a flow shop environment, the objective is to batch the jobs and sequence the batches such that the makespan is minimized.

Published
2021

3. PSO for Minimizing Makespan of Non-Identical Parallel Batch Processing Machines

Author

Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Damodaran, Purushothaman, Diyadawagamage, Don Asanka, Mario C. Vélez-Gallego, Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Damodaran, Purushothaman, Diyadawagamage, Don Asanka, and Mario C. Vélez-Gallego

Abstract

Environmental Stress Screening (ESS) chambers are commonly used to test Printed Circuit Boards (PCBs) to detect early failures before they are used in the field. This research is motivated by our interactions with an electronics manufacturer

Published
2021

4. Minimizing Total Weighted Tardiness on a Batch-Processing Machine with Non-Identical Job Sizes and Non-Zero Ready Times

Author

Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Mario C. Vélez-Gallego, Maya, Jairo, Purushothaman, Damodaran, Universidad EAFIT. Departamento de Ingeniería de Producción, Gestión de Producción y Logística, Mario C. Vélez-Gallego, Maya, Jairo, Purushothaman, and Damodaran

Abstract

This research was motivated by a practical application observed at an electronics manufacturing facility in which meeting customer due dates is the primary objective. Each job to be scheduled is defined by its processing time, ready time, due date

Published
2021

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