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This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

This paper presents a novel modeling and analysis of inter-symbol interference (ISI)jitter in serial data channels either between chips or on chip. The simulation results show that ISI jitter is dependent on pole location, settling time, and damping ratio of the data serial channel. Based on the proposed ISI jitter model, the effect of the ISI jitter on other jitter components is illustrated along with realistic simulation results.