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We have proposed and been developing a new broad-band terahertz (THz) radiation detector using a Nb-based superconducting tunnel junction (STJ). The STJ's were fabricated on LiNbO/sub 3/ and LiTaO/sub 3/ mono-crystal substrates. We radiated monochromatic THz pulses in the range 1-2 THz with the pulse repetition rate of 49 Hz, and successfully detected the corresponding periodic signals via a charge-sensitive preamplifier. The current signal obtained by the derivative of the output signal gave the time response of about 15-20 microseconds. The frequency response was compared with that of a conventional pyro-electric sensor. We found their frequency response showed the similar shape in frequency, demonstrating the flat response of the STJ detector in 1-2 THz. These results show that the detector can be used as a broad-band THz and far-infrared radiation detector above the frequency corresponding to the energy gap of the superconductor used for the base electrode.

Photosensitive polyimide insulation layers have been introduced to fabricate superconducting integrated circuits. It is shown to simplify the fabrication process, because the photosensitive polyimide insulation layer can be patterned by conventional photolithography process, resulting in the etching process unnecessary in the present new fabrication process. Three kinds of contact hole (junction top electrode contact, junction base electrode contact, and resistor contact) are simultaneously formed in the photolithography process of the polyimide. A minimum contact hole size is designed to be 1.5 /spl mu/m square for a 3 /spl mu/m /spl times/ 3 /spl mu/m squared junction. Superconducting current density of 2.4/spl times/10/sup 6/ A/cm/sup 2/ of the contact hole was measured. Palladium resistors were successfully made with through hole contacts of the photosensitive polyimide insulation layer. We demonstrated superconducting integrated circuits using this new fabrication process including the minimum 3 /spl mu/m /spl times/ 3 /spl mu/m squared Nb/Al-AlO/sub x//Nb Josephson tunnel junction. The circuit operation is also demonstrated in the fabricated superconducting integrated circuits with the photosensitive polyimide insulation layers.

We have studied normal-distribution-shaped Josephson tunnel junctions for STJ (superconducting tunnel junction) photon detector applications. By employing a normal-distribution function to the shape of the superconducting electrodes sidelobes of the Josephson current were entirely suppressed with a small magnetic field. This behavior was confirmed experimentally by using Nb/AlO/sub x//Nb Josephson tunnel junctions. There were no oscillatory sidelobes in the Josephson current dependence on the magnetic field. Experimental results were in good agreement with theoretical ones. The Josephson current was efficiently suppressed by an external magnetic field of about 0.5 mT at 4.2 K, which is less than one tenth that of other shaped junctions. In the experiment at 0.3 K, Fiske steps due to the resonances were not observed by suppression with a magnetic field of about 1 mT.

We have fabricated YBaCuO crossover using CeO/sub 2/ insulating film as high-T/sub c/ multilayer structure. The bottom YBaCuO bridges showed good critical temperature T/sub c/ of 87 K and critical current density J/sub c/ of 1.0/spl times/10/sup 5/ A/cm/sup 2/. The top YBaCuO bridges, however, showed lower J/sub c/ than the bottom YBaCuO, since the grain boundaries were formed at the step edges of the bottom bridge. The crossover structures have a resistivity of more than 1/spl times/10/sup 8/ /spl Omega//spl middot/2 cm below 80 K, indicating superior insulating properties of the CeO/sub 2/ layer. In order to improve J/sub c/ of the top YBaCuO bridges, we have also studied the properties of YBaCuO bridges on CeO/sub 2/ film bank. It is found that J/sub c/ of the top bridges was not only dependent on the step height, but also depends on the YBaCuO thickness. In order to improve J/sub c/ of the top bridges, lower step height and thicker YBaCuO films are required.

We have developed a phononmediated radiation detector using Nb-based superconducting tunnel junctions (STJs). The STJs are fabricated on a substrate as an absorber of the radiation, and a substantial amount of emergent phonons with an energy above the energy gap are detected. The performance of the detector depends on the collection efficiency of the phonons. A selection of an appropriate substrate is required for optimizing the detector performance. We fabricated Nb-based STJs on a Al/sub 2/O/sub 3/ and a LiNbO/sub 3/ substrates, and compared the pulse heights of substrate phonon events due to X-ray irradiation to the substrates. We found that the maximum pulse height of the phonon events for the LiNbO/sub 3/ substrate was about twice of that for the Al/sub 2/O/sub 3/ substrate, so that these spectra which was obtained from two STJs showed different shapes, especially the peak due to phonon events.

We have fabricated Nb-based superconducting tunnel junctions (STJs) with Al trapping layers using the photosensitive polyimide insulation layer for X-ray detector. It is possible to simplify the fabrication process of the STJs, because the photosensitive polyimide is used as the insulation layer instead of conventional inorganic insulation films without an etching process in a vacuum chamber. The polyimide insulation layer expects to be stable for thermal cycling between 0.3 K and room temperature. The preliminary experiments of 5.9 keV radiation shows the energy resolution of 86 eV.

We have investigated subgap characteristics of Nb/AlOx/Nb tunnel junctions with high critical current density (high-J/sub c/). A good agreement of the experimental data with the solution of Werthamer's equation clearly shows that steep current steps observed at odd submultiples of the gap voltage, which cannot be explained by multiparticle tunneling and/or multiple Andreev reflection, are mainly caused by Josephson self-coupling. Our experimental results suggest that Josephson self-coupling is important to high-J/sub c/ tunnel junctions. >

It is important to develop a reliable and reproducible fabrication process of submicron Nb/AlO/sub x//Nb Josephson junctions to improve the integration level and the operating speed of the Josephson LSI circuit. For this purpose, we have developed an improved etching process by introducing a dummy etching process and using a scanning electron microscope (SEM) as an etching end-point detector. The dummy etching process improves the anisotropy of a reactive ion etching (RIE) process using CF/sub 4/. The etching residue around a junction is detected easily and correctly by the SEM observation. We have successfully fabricated Nb/AlO/sub x//Nb Josephson junctions with critical current density of 10/sup 4/ A/cm/sup 2/ using the cross-line patterning (CLIP) method and electron beam lithography, where the junction size was varied from 2 /spl mu/m to 0.5 /spl mu/m at 0.1 /spl mu/m intervals. High-quality submicron junctions for integrated circuits with suitable critical current variations were obtained. >

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed. >

The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1. >

A 16 kb Josephson RAM (random access memory) has been designed using a miniaturized variable threshold memory cell based on a 2 mu m Nb/Al-oxide/Nb junction technology. By using a novel strip-line structure for the inductance of the superconducting quantum interference device (SQUID) type selection gate, the miniaturized cell occupies 14 mm 28 mu m, just 20% of the area of a previous cell designed with a 3 mu m rule. OR-INVERT type address decoders are constructed with a new 4JL (four-junction logic) gate with a fan-out of four. The whole circuit occupies a 3.1 mm*5.0 mm area. The access time is evaluated to be 475 ps, with a total power dissipation of 7.3 mW/chip. Based on these performance data and data from a previous 1 kb RAM experiment, the prospects for Josephson VLSIs are discussed. >

An improved fabrication process for submicron NbN/MgO/NbN Josephson tunnel junctions has been developed. By introducing a contact layer between the junction and the wiring layer, the critical current of the wiring above the junction was considerably enhanced. A logic circuit composed of four-junction logic gates was fabricated using 0.9- mu m-square junctions. Logic delay measurement was successfully achieved with a minimum logic delay of 3.6 ps/gate and a wide operating margin of +or-17% within 50 gates. >

The first computer operation of a 4-b Josephson computer, ETL-JC1 (Electrotechnical Laboratory-Josephson Computer no.1), designed using a reduced instruction set computer (RISC) architecture is described. In the experiment, the computer functions have been verified by executing a computer program installed in a Josephson read-only memory (ROM) at a low repetition frequency. To construct the computer, four Josephson LSI chips including a register and arithmetic logic unit, a sequence control unit, an instruction 1280-b ROM unit, and a 1-kb RAM unit were connected on a nonmagnetic printed circuit board. The Josephson LSI chips were fabricated using Nb/AlO/sub x//Nb tunnel junctions with 3- mu m design rules. The total power dissipation was 6.2 mW in the total circuit, which consists of 22000 junctions including regulators on every chip. On the basis of measurements of the delay times of the logic gates and the access times of the memory chips, it is expected that the program execution in the critical path can be carried out with a single central processing unit in less than 1 ns, resulting in 1 giga-instructions per second (GIPS). >