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This work studies how to estimate the mean-field density of large-scale systems in a distributed manner. Such problems are motivated by the recent swarm control technique that uses mean-field approximations to represent the collective effect of the swarm, wherein the mean-field density (especially its gradient) is usually used in feedback control design. In the first part, we formulate the density estimation problem as a filtering problem of the associated mean-field partial differential equation (PDE), for which we employ kernel density estimation (KDE) to construct noisy observations and use filtering theory of PDE systems to design an optimal (centralized) density filter. It turns out that the covariance operator of observation noise depends on the unknown density. Hence, we use approximations for the covariance operator to obtain a suboptimal density filter, and prove that both the density estimates and their gradient are convergent and remain close to the optimal one using the notion of input-to-state stability (ISS). In the second part, we continue to study how to decentralize the density filter such that each agent can estimate the mean-field density based on only its own position and local information exchange with neighbors. We prove that the local density filter is also convergent and remains close to the centralized one in the sense of ISS. Simulation results suggest that the centralized suboptimal density filter is able to generate convergent density estimates, and the local density filter is able to converge and remain close to the centralized filter., arXiv admin note: text overlap with arXiv:2009.05366

This paper obtains fundamental limits on the computational precision of in-memory computing architectures (IMCs). An IMC noise model and associated SNR metrics are defined and their interrelationships analyzed to show that the accuracy of IMCs is fundamentally limited by the compute SNR ($\text{SNR}_{\text{a}}$) of its analog core, and that activation, weight and output precision needs to be assigned appropriately for the final output SNR $\text{SNR}_{\text{T}} \rightarrow \text{SNR}_{\text{a}}$. The minimum precision criterion (MPC) is proposed to minimize the ADC precision. Three in-memory compute models - charge summing (QS), current summing (IS) and charge redistribution (QR) - are shown to underlie most known IMCs. Noise, energy and delay expressions for the compute models are developed and employed to derive expressions for the SNR, ADC precision, energy, and latency of IMCs. The compute SNR expressions are validated via Monte Carlo simulations in a 65 nm CMOS process. For a 512 row SRAM array, it is shown that: 1) IMCs have an upper bound on their maximum achievable $\text{SNR}_{\text{a}}$ due to constraints on energy, area and voltage swing, and this upper bound reduces with technology scaling for QS-based architectures; 2) MPC enables $\text{SNR}_{\text{T}} \rightarrow \text{SNR}_{\text{a}}$ to be realized with minimal ADC precision; 3) QS-based (QR-based) architectures are preferred for low (high) compute SNR scenarios., Comment: 14 pages, 13 figures

Cost-friendly differential privacy (CDP) of smart meters can be preserved by an appropriate charging and discharging mechanism that uses rechargeable batteries (RBs) to generate Laplace distributed random noise. However, the existing CDP methods have several issues. Firstly, the maximum discharge rate of an RB requires to vary with the maximal consumption of houses. Secondly, the probability of an RB to charge/discharge depends on the demand, regardless of the state of charge (SoC) of an RB. Thirdly, in extreme SoC (near-empty or almost fully charged) of an RB, no noise added to the demand. To overcome these, we propose a mechanism in which a novel probability density function is designed to generate near Laplace distributed random noise. We also utilize a renewable energy source with small storage in cascade with an RB to enhance performance. Both theoretical analysis and simulations are performed to demonstrate the effectiveness of our proposed method.

Following recent advancements in Terahertz (THz)technology, THz communications are currently being celebrated as key enablers for various applications in future generations of communication networks. While typical communication use cases are over medium-range air interfaces, the inherently small beamwidths and transceiver footprints at THz frequencies support nano-communication paradigms. In particular, the use of the THz band for in-body and on-body communications has been gaining attention recently. By exploiting the accurate THz sensing and imaging capabilities, body-centric THz biomedical applications can transcend the limitations of molecular, acoustic, and radio-frequency solutions. In this paper, we study the use of the THz band for body-centric networks, by surveying works on THz device technologies, channel and noise modeling, modulation schemes, and networking topologies. We also promote THz sensing and imaging applications in the healthcare sector, especially for detecting zootonic viruses such as Coronavirus. Wepresent several open research problems for body-centric THz networks.

Switched capacitor circuits exhibit dynamic topology and operate on clock phase dependent charge transfer. A circuit simulator that can directly compute branch charges by retaining capacitors and closed switch branches while excluding open switch branches based on clock is proposed in this work. Topological/graph-based formulation is used for charge level analyses of ideal switched capacitor circuits. The simulator supports time, frequency, noise and sensitivity analyses of switched capacitor circuits for any number of clock phases. The compact linear difference equation can compute time responses in a straightforward manner while frequency analysis is based on the impulse response of the circuit. Adjoint network concept is used to perform noise and sensitivity analyses for computing noise spectrum and differential derivatives respectively. The same formulation holds good for the adjoint equivalent network also since the network topology and incidence matrix almost remains same. Simulation results are presented for sample circuits to demonstrate the performance of the proposed simulator. Time and frequency responses have been compared with SWITCAP while noise and sensitivity responses with a commercial simulator.

We investigate state estimation of linear systems over channels having a finite state not known by the transmitter or receiver. We show that similar to memoryless channels, zero-error capacity is the right figure of merit for achieving bounded estimation errors. We then consider finite-state, worst-case versions of the common erasure and additive noise channels models, in which the noise is governed by a finite-state machine without any statistical structure. Upper and lower bounds on their zero-error capacities are derived, revealing a connection with the topological entropy of the channel dynamics. Separate necessary and sufficient conditions for bounded linear state estimation errors via such channels are obtained. These estimation conditions bring together the topological entropies of the linear system and the discrete channel.

To further mitigate the BER error floor of M-ary differential chaos shift keying modulation for impulsive noise, a low-cost high-reliability coded modulation scheme without equalizations is desirable for impulsive noise. In this paper, a protograph-based low-density parity-check coded MDCSK-based bit-interleaved coded modulation scheme is proposed for the scenario with impulsive noise. Considering the Gaussian distribution of protograph extrinsic information transfer and the benchmark of coding design, the U-shaped non-coherent capacity is derived with optimal code rate for square MDCSK, showing that the code rates are stable with E_b/N_0 increasing but still much lower than that of DS-16DQAM at code rate >0.145. The derived joint probability density function can be considered as approximately a Gaussian distribution, which is used to improve the impulsive noise fitted PEXIT. Finally, a new code under a novel principle is designed for better bit error rate performance based on the improved PEXIT analysis. Both PEXIT analysis and simulation results demonstrate that the proposed scheme achieves a better BER than that with a traditional scheme, and suggesting a research approach based on simple methods. This basic research work provides a guide to establish a framework and optimize the performance of transmission systems over practical power line communication.

The learning control strategy is studied for networked stochastic systems, where the output and input data are transmitted through multiple independent fading channels. The traditional P-type learning control scheme is revised according to the specific fading positions, where the constant learning gain is replaced by a variable one to suppress the effect of various uncertainties. Strong convergence of the proposed scheme is established under random fading phenomena and system noise. The input error is shown convergent to zero as the cycle number increases. Two numerical examples demonstrate the applications of the proposed scheme.

OBJECTIVE: Diffuse correlation spectroscopy (DCS) is an optical technique that allows for the non-invasive measurement of blood flow. Recent work has shown that utilizing longer wavelengths beyond the traditional NIR range provides a significant improvement to signal-to-noise ratio (SNR). However, current detectors both sensitive to longer wavelengths and suitable for clinical applications (InGaAs/InP SPADs) suffer from suboptimal afterpulsing and dark noise characteristics. To overcome these barriers, we introduce a cross correlation method to more accurately recover blood flow information using InGaAs/InP SPADs. METHODS: Two InGaAs/InP SPAD detectors were used for during in vitro and in vivo DCS measurements. Cross correlation of the photon streams from each detector was performed to calculate the correlation function. Detector operating parameters were varied to determine parameters which maximized measurement SNR. State-space modeling was performed to determine the detector characteristics at each operating point. RESULTS: Evaluation of detector characteristics was performed across the range of operating conditions. Modeling the effects of the detector noise on the correlation function provided a method to correct the distortion of the correlation curve, yielding accurate recovery of flow information as confirmed by a reference detector. CONCLUSION: Through a combination of cross-correlation of the signals from two detectors, model-based characterization of detector response, and optimization of detector operating parameters, the method allows for the accurate estimation of the true blood flow index. Significance: This work presents a method by which DCS can be performed at longer NIR wavelengths with existing detector technology, taking advantage of the increased SNR.

A 320 x 240 indirect time-of-flight (i-ToF) image sensor with a 5.6-μm two-tap 1.5-V pump gate modulation pixel has been designed. Novel characteristics, such as the optimized pinned layer doping and potential buffer region (PBR) structure with pump gate modulator (PGM), are proposed to achieve a maximum lateral modulation electric field of 1500 V/cm under the front-side illumination (FSI) process. As a result, the proposed time-of-flight (ToF) sensor shows 200-mW power consumption and 54% demodulation contrast (DC) at 50-MHz modulation frequency, depth noise less than 1% with 940-nm illuminator from 0.3 to 3 m.

In this paper, the design considerations and basic equations related to thick-film screen-printed sensing devices are included. The geometry of the device and the patterns of the functional sensing film, or of the electrodes are taken into account for the determination of the operational frequency, noise voltage, quality factor and other key parameters, related to the proper work of the resistive, capacitive and surface acoustic wave based sensors. The determination of some parasitic components and possible errors is also provided. The focus is put on the most widely spread coating patterns related to this technology – meander and comb-shaped. The technology flow chart of the screen-printing technology is given and the approaches for fine-tuning the resistance at the thick-film resistive sensors are discussed. Comparison of the typically used materials for substrates, resistive, conductive, and dielectric coatings is made. Criteria for the selection of the different pastes or inks for specific applications are mentioned.

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator's figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-E oscillator is implemented in a 0.18-μm CMOS technology. At 4 GHz, it exhibits a phase noise of -152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².

In this paper, we consider the application of a cell-free (CF) Massive multiple input multiple output (MIMO) system to low power Internet of things (IoT) networks. CF Massive MIMO distributes many access points (APs) in a given area, and supports many IoT devices simultaneously using the same time and frequency resources. To support many IoT devices that have more than the number of service antennas within limited coherence time/frequency, reference signal (RS) should be reused. Generally, CF Massive MIMO with massive connectivity requires a lot of power, and thus it is difficult to use in low power IoT networks. In this regard, we propose an energy efficient (EE) power control scheme that can significantly reduce the radiation power of IoT devices. We notice that with many IoT devices, there is a quite large amount of interference, and if we choose the radiation power based on this information, the signal-to-interference plus noise ratio (SINR) becomes approximately independent of the radiation power. We show that our scheme can reduce the radiation power more than 90% compared to normal operation. We also show that with many IoT devices, there is SE hardening effect, and maximum ratio (MR) processing and minimum mean square error (MMSE) processing present similar performance, and thus MR processing could be sufficient for use in CF Massive MIMO with massive IoT connectivity.

This article presents an inherent gain error-tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the pipeline, realizing an N-0 (2-0) multistage NS sigma-delta (MASH). The Nth order from the first stage shapes not only the quantization error and comparator noise but also the interstage gain and nonlinearity error, which greatly relaxes the gain accuracy constraint in the conventional pipelined architecture. In addition to gain, a code-counter-based (CCB) background offset calibration is introduced to mitigate the interstage offset with low cost. The prototype further adopts partial interleaving in the first stage for high speed while sharing the integration capacitors in the feed-forward (FF) structure for a compact area. The 2-0 MASH runs at 400 MS/s and achieves 25-MHz bandwidth with 8 x OSR, consuming 1.26-mW power from a 1-V supply. Within a gain error range of -16% to +12%, the SNDR of the ADC deviates less than 3 dB from the nominal 75-dB SNDR. Fabricated in a 28-nm CMOS process, it exhibits a 178-dB Schreier figure of merit (FoM ${_{{S}}}$ ).

Occurrence of high frequency emission due to increasing use of power electronic based equipment challenges the functioning of equipment, e.g., malfunctions of equipment, audible noise or performance/lifetime degradation of dc-link capacitor. When subjected to a high frequency voltage distortion, an AC-DC converter draws intermittent current of the same frequency, this is referred to as 'intermittent conduction'. In this paper, a link between intermittent conduction and dc-link capacitor current has, for the first time, been constituted through a mathematical expression. Based on this, a model that can quantify the impacts on dc-link capacitor and calculate maximum allowed voltage in the frequency range of 2-150 kHz, so called 'supraharmonics' (SHs), has been proposed for avoiding degradations. Besides modelling, a testing technique is implemented where maximum allowed voltage can be identified for an equipment under test (EUT). The result shows that dc-link capacitor's stress can be managed under the SHs if maximum SH voltages are respected. The proposed model gives a better understanding of SH impacts on dc-link capacitor and the mechanisms behind. The study has been limited to equipment that draws input current lower than 16 A as they exhibit more non-linear characteristic and longer zero-crossing which results in intermittent conduction.

This work presents a 300-GHz low-noise amplifier (LNA) in a SiGe:C 130-nm BiCMOS technology, featuring $f_{t}$/$f_{max}$ of 470/700 GHz. The designed amplifier uses three cascaded stages in a pseudo-differential cascode topology with input and output baluns facilitating single-ended measurements. The first stage is matched trading off noise and gain performance, while a T-type output matching network is used for broadband matching. The interstage matching is performed using center tap transformers. On-wafer measurements show that the designed LNA has a peak small-signal gain of 10.8 dB at 325 GHz, along with a 3-dB bandwidth of 68 GHz and an input 1-dB compression point of -15.6 dBm at 287.5 GHz. The simulated noise figure is better than 12.7 dB over the required band. The circuit occupies 0.26-mm² silicon area and consumes 119 mW from a 3.3-V supply.

As more compact designs and more assembled function modules are utilized in modern electronic devices, radio-frequency interference (RFI) source reconstruction is becoming more challenging because different noise sources may contribute simultaneously. This article presents a novel methodology to reconstruct multiple random noise sources on a real-world product, including several double-data-rate (DDR) memory modules and a high-speed connector. The DDR modules located beneath a heatsink cause random noise-like signals, which renders phase measurements challenging. An approach based on the tuned-receiver mode of a vector network analyzer is developed to measure the field phase from the random DDR signals, which can be further modeled with a Huygens’ box using the measured field magnitude and phase. Moreover, the connector can be modeled using an equivalent magnetic dipole. Furthermore, the total RFI power from the DDR memory modules and the high-speed connector, which generate uncorrelated RFI noise, is found to equal the summation of the individual power values obtained by an root mean square detector, which can be mathematically corroborated. Using the proposed method, the reconstructed source model can predict RFI values close to measurement results with less than 5 dB deviation.

We present an OTA-free 1-1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

The multi-mode noise is an important issue for the optoelectronic oscillator (OEO) in generating a spectrally pure microwave. Especially in oscillators with low phase noise, increasing the cavity length to improve the phase noise performance will make the mode interval smaller, which is more likely to cause multi-mode noise. Here, we proposed a low phase noise and high side-mode suppression ratio self-injection-locked OEO based on frequency conversion filtering. We theoretically and experimentally studied the influence of the phase noise of the external microwave source on the proposed OEO and, as a comparison, the conventional injection-locked OEO. The results show that, compared with the traditional injection-locked OEO, the proposed OEO is less sensitive to the phase noise of the external microwave source. Under the same experimental conditions, the proposed OEO achieved the same side-mode suppression ratio and the phase noise is reduced by 30 dB at 10 kHz offset from the 10-GHz carrier compared with the conventional injection-locked OEO.

The output tracking control problem is investigated in this article. First, a new tradeoff performance index is presented for single-input-multioutput (SIMO) systems. Based on the frequency-domain method, the tracking performance limitations under time delay, packet loss, and channel noise effects are derived. We use a bivariate stochastic process to model the packet loss, and assume that channel noise is additive white Gaussian noise (AWGN). Two explicit expressions of the best tradeoff performance are given with the single-degree-of-freedom (SDOF) and two-degree-of-freedom (TDOF) control structures. It is shown that the tracking control performance has a close relation with the intrinsic characteristic of the plant, as well as the time delay, packet-dropouts rate, and power spectral density of AWGN. We also demonstrate that compared with the SDOF control structure, the TDOF control structure can improve the systems' attainable performance. A simulation example is finally discussed to validate the conclusions.

This paper describes the design, fabrication, and record performance of a new class of ultra-wideband wavelength tuning, ultra-low noise semiconductor laser, the Integrated Coherent Tunable Laser (ICTL). The ICTL device is designed for, and fabricated in, a CMOS foundry based Silicon Photonics platform, utilizing heterogeneous integration of III-V material to create the integrated gain section of the laser - enabling high-volume mass-market manufacturing at low cost and with high reliability. The ICTL incorporates three or more ultra-low loss micro-ring resonators, with large ring size, in a Sagnac loop reflector geometry, creating exceptional laser reflector performance, plus an extended laser cavity length that enables highly-coherent output; ultra-low linewidth and phase noise. This paper describes record integrated laser performance; 118 nm wavelength tuning, covering S-, C- and L-bands, with Lorentzian linewidth

This paper reports a high-performance, low-power temperature sensor suitable for wireless IoT devices/RFID tags. The system utilizes a mostly digital approach to achieve energy-efficient, sub-μW operation with a resistor-based temperature sensor. A sampled, incomplete-settling, switched-capacitor-based Wheatstone bridge is read out using a digital frequency-locked loop (DFLL) while harnessing the quasi-periodic limit cycles to reduce in-band noise. Implemented in a 65 nm CMOS process, it consumes 310 nW and achieves 9.8 mK resolution in a 10 ms conversion time. This results in a 297 fJ∙K2 figure-of-merit (FoM) and low energy (3.1 nJ/meas.).

This brief presents a class-C voltage-controlled oscillator (VCO) that ensures a robust start-up with low phase noise and high power efficiency. The proposed start-up scheme, which uses a voltage converter that operates according to the output state, relieves the start-up difficulty by supplying a timevarying bias voltage to the core transistors and allows the VCO to operate in an optimal state. The start-up circuitry is enabled only during initial operation, so power efficiency is improved without phase noise degradation. Furthermore, a capacitor array with a high quality factor is implemented by a direct capacitor connection that exhibits low series resistance. Fabricated with a 65-nm CMOS, the VCO demonstrates a frequency tuning range of 13.1% from 19.3 to 22.0 GHz. The measured minimum phase noise at a 1-MHz offset is --106.33 dBc/Hz at an oscillation frequency of 19.7 GHz, while dissipating 3.8-mW of power from a 1.0-V supply. The VCO occupies an active area of 0.064 mm2. It reveals a figureof-merit and figure-of-merit with area of --186.4 and --198.3 dBc/Hz, respectively.

The switching action of power electronic devices causes high frequency current, magnetic field, vibration and annoying noise of induction machines fed by inverters, and these high-frequency components concentrate around the switching frequency and its multiple times. Adding auxiliary winding with capacitors is an effective way to reduce the high frequency vibration by weakening the high frequency magnetic field. In order to analyze the vibration mitigation effect of adding auxiliary winding with capacitors, this method is systematically and theoretically analyzed in the paper. The accurate equivalent circuit of induction machines with auxiliary winding is proposed considering the mutual leakage inductance between stator main winding and auxiliary winding. The transfer function of electromotive force and its frequency response are used to illustrate the effect of vibration reduction. To verify the correctness of the analysis, two induction machines with different auxiliary winding arrangements are prototyped and tested.

An ultra-small-area, low-power analog front-end (AFE) for high-density neural recording is presented in this paper. It features an 11-bit incremental delta-sigma analog-to-digital converter (σ ADC) enhanced with an offset-rejecting event-driven input biasing network. This network avoids saturation of the ADC input caused by leakage of the input-coupling capacitor implemented in an advanced technology node. Combining AC-coupling with direct data conversion, the proposed AFE can tolerate a rail-to-rail electrode offset and achieves a good trade-off between power, noise, bandwidth, input impedance, and area. Fabricated in a 22-nm fully-depleted silicon on insulator (FDSOI) process, the design occupies an active area of

This paper presents a TIA topology with an active feedback path and a current bleeding circuit to relax the tradeoffs among gain, bandwidth and headroom limitations in a low voltage design. Using a two-stage common-source amplifier in the feedback path creates adequate degrees-of-freedom in the design for lowering the input resistance of the TIA and improving the bandwidth without degrading the amplifier gain. Analysis of the TIA transfer function and noise provide design guidelines for a well-behaved time response and low input-referred current noise. To demonstrate efficiency of the proposed technique, two designs in 0.18 μm CMOS technology with different values of the input capacitor are presented. The comparison of the designs with two categories of TIAs reported in the literature validates effectiveness of the presented transconductance boosting technique and demonstrates the flexibility of the proposed topology for different applications with a vast variety of the capacitance values at the TIA input.

CMOS single-photon avalanche diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations demonstrate the improved PDP with the simple addition of a single existing implant, which allows for an engineered performance without modifications to the process. The result is an 8.8 $\mu$ m diameter SPAD exhibiting $\sim$ 2.6 cps/ $\mu$ m $^2$ DCR at 20 $^{\circ}$ C with 7 V excess bias. The improved structure obtains a PDP of 62% and $\sim$ 4.2% at 530 nm and 940 nm, respectively. Afterpulsing probability is $\sim$ 0.97% and the timing response is 52 ps FWHM when measured with integrated passive quench/active recharge circuitry at 3 V excess bias.

Leakage current issues are worthy of attention for non-isolated grid-connected systems. This paper introduces the method of eliminating common-mode (CM) voltage and reducing the leakage current based on modulation, and analyzes the correlation between actual effects of the method and the flying capacitor (FC) voltage balance in three-phase three-level FC grid-connected inverter. The proposed carrier-based modulation can balance the FC voltage by changing the transmission sequences of pulses and theoretically achieve zero CM voltage. In order to deal with the low frequency fluctuation and bias voltage of FC caused by asymmetry of actual hardware, the control method is introduced, which controls FC voltage by changing the action times distribution of switches, while still eliminating the CM voltage. Simulation and experimental results are provided to validate that the proposed method can control FC voltage and achieve good performance in suppressions of CM voltage, leakage current and CM EMI noise.

With superb device characteristics, gallium nitride (GaN) power transistors facilitate fast and efficient power conversion and delivery in modern power circuits. To take full advantage of these devices, high switching frequency ( $f_{{SW}})$ operation is highly desirable. However, the lack of GaN compatible high-speed, efficient, and reliable gate drivers has been a formidable design hindrance. In this article, we address three critical design challenges faced in GaN power gate driving, namely bootstrap (BST) level-shifting, switching slew rate (SR) control, and active deadtime $t_{{dead}}$ control. We first propose a BST dynamic level-shifting technique to enable sub-nanosecond $t_{{delay}}$ at high $f_{{SW}}$ . Meanwhile, a dual-SR switching technique is introduced to retain both low switching power and noise. Compared with traditional constant $t_{{dead}}$ controls, the $t_{{dead}}s$ in this design are regulated actively for high efficiency. To validate these techniques, a four-phase GaN-based switching power converter was designed and implemented on a 0.35 μm high-voltage (HV) BCD process. At a $f_{{SW}}$ of 20 MHz and a $V_{{IN}}$ of 20 V, it delivers a maximum power of 8.4 W and a peak efficiency of 84.9%. The gate drivers are fully integrated including all BST capacitors and active BST switches. It achieves regulated rise and fall $t_{{dead}}s$ of 3.2 and 4.7 ns, respectively, for a load range from 50 mA to 1.2 A. The gate switching rise time $t_{R}$ is reduced to 1 ns with a maximum switching SR of 48 V/ns. The converter employs a HV synchronized hysteretic control, which works with the proposed gate drivers seamlessly to demonstrate a dynamic voltage scaling (DVS) Vo up- and down-tracking speeds of 0.33 μs/V and 0.47 μs/V, respectively.

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where nonlinearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, Ieff model. The Ieff is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and Ieff of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topologybased and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime.

Three-dimensional (3-D) massive multiple-input-and-multiple-output (MIMO) systems, which explore degrees of freedom in both the vertical and the horizontal dimensions, are a promising technology to enhance spectral efficiency in the next-generation communication systems. As an emerging modulation technology with millimetre wave (mm-wave) communication in massive MIMO systems with limited radio-frequency (RF) chains, the spatial scattering modulation (SSM) makes use of beamspace domain resources to further improve the spectral efficiency. However, most published works on the SSM only focus on two-dimensional (2-D) MIMO systems. In this paper, we generalize the SSM system to 3-D space. First, we design a novel generalized 3-D SSM system by considering both vertical and horizontal angles to determine scattering paths, which are selected to convey information bits. Then, we propose a whitening filter based optimal detection algorithm to detect the received symbols with correlated noise, where the correlation is generated by the combination of the received signals from the large-scale planar receiving antenna array. Next, we design a 2-D fast Fourier transform (FFT) based transceiving approach to improve the hardware friendliness. After that, we propose a low-complexity detector based on the linear minimum mean square error (MMSE) detection algorithm. Moreover, we derive the union upper bound on average bit error probability (ABEP) in a closed form and the asymptotic performance expression for the generalized 3-D SSM system. Finally, we analyse the impact of transmission environment on the ABEP performance. Numerical results show that the generalized 3-D SSM system outperforms the conventional 2-D SSM system, which reduces the ABEP by 10× with the same signal-to-noise ratio (SNR) level under the typical indoor environment.

Backscattering noise is a key factor to restrict the performance of resonant fiber optic gyroscopes(RFOG). In order to improve the accuracy of RFOG, this paper proposes a scheme with heterodyne optical phase-locked loop(HOPLL) technique based on acousto-optic modulation(AOM) to suppress backscattering noise. In this scheme, the main light source is divided into three output lights, two of which are frequency-shifted by the AOM, and then they are phase-locked with the third light, using the HOPLL technique. The two channels of frequency-shifted light are respectively used as the clockwise (CW) and counterclockwise(CCW) light of the RFOG, and are locked on the resonance peak. The transmissive fiber resonator can be regarded as a band-pass filter. By adjusting the reference signal in the HOPLL, the carrier of the two frequency-shifted lights can be moved away from the resonance peak. The carrier light intensity of the frequency-shifted light is suppressed by the cavity itself. The suppression ratio(SPR) reaches 15.83dB. The experimental results illustrate that the bias stability of RFOG is 3.8/h based on the Allan deviation, strongly proving the effectiveness of this scheme in suppressing backscattering noise in practical applications.

MEMS-based magneto-resistive (MR) sensors have attracted considerable attention for years due to their small weight, low power consumption, and high sensitivity, whereas the 1/f noise is larger in the low-frequency region and degrades the low-frequency magnetic field detection limit. To reduce the impact of 1/f noise, MEMS resonators are utilized to modulate the low-frequency field to a high-frequency region where the 1/f noise vanishes. This paper proposes a novel modulation method called synchronous motion modulation (SMM) using a comb-driven resonator and a piezoelectric cantilever resonator, meanwhile analyzes the relationship of modulation efficiency of SMM, vertical motion modulation (VMM), and gap change modulation (GCM) theoretically and with finite element method (FEM) simulation. The results show that the theoretical analysis is coincident with numerical simulation, and the SMM is the optimal modulation method for improving the low-frequency magnetic field detection limit due to its modulation efficiency is the sum of that of VMM and GCM.

In magnetic nanoparticle tomography (MNT), the reduction of artefacts and the calculation time can be used to estimate the position of magnetic nanoparticles (MNPs). Non-negative least squares (NNLS) inverse problem analysis has been used in MNT systems for this task. However, owing to the presence of measurement noise and the high sensitivity of the NNLS method, it often estimates certain MNPs inaccurately, i.e., it generates artefacts. In addition, its calculation time is very high. In this study, we applied the minimum variance spatial filter (MV-SF) inverse problem analysis to MNT and estimated the position of an MNP sample containing 100 μ g of Fe. Using the MV-SF method, MNP samples placed at a depth of 25–40 mm were observed to have no artefacts. Moreover, the MV-SF method was also observed to be faster than the NNLS method by a factor of approximately 20. These results verify the feasibility of the MV-SF method for estimating the MNP positions in an MNT system.

In this article, a novel circuit is proposed to synthesize absorption common-mode filters (A-CMFs) in only one stage, which can be implemented with different kinds of transmission lines. This proposed one-stage absorption circuit has been derived with analytical equations, and design formulas are found to determine circuit parameters. To validate the proposed circuit and derived formulas, an intuitional structure composed of a meander slotline (MSL), a straight differential pair, and one resistor is proposed. Moreover, a technique named meander asymmetrical coplanar strip (MACPS) has also been developed to reduce the size of MSL-type A-CMF by up to 26%. Finally, the proposed test sample of MACPS-type A-CMF is fabricated in a two-layer printed circuit board (PCB) and measured. The common-mode (CM) noise absorption efficiency of above 80% can be obtained from 2.33 to 2.67 GHz to eliminate CM noises in the Wi-Fi 2.4 GHz band. Besides, the MACPS-type A-CMF provides an excellent differential-mode (DM) signal integrity. The −3 dB bandwidth of DM insertion loss can reach 7.5 GHz, and the measured eye diagram of the proposed work is identical to that of the reference board even the transmitted data rate is up to 16 Gb/s. To our best knowledge, the smallest A-CMF implemented in a two-layer PCB is achieved in this article with the electrical dimension being only 0.0358 λg2.

This brief presents a compact variable gain amplifier (VGA) with continuous time-gain compensation (TGC) for ultrasound imaging. The proposed VGA utilizes an open-loop topology and transconductance-subtraction load for compact implementation with sufficient gain range. To compensate for gain nonlinearity of VGA, this work proposes a systematic predistortion of gain-control signal to enhance an accuracy of TGC operation. The proposed VGA implemented in 180-nm CMOS process occupies 0.025 mm2, and consumes 0.96 mW for the maximum gain condition with a supply voltage of 1.8 V. A real-time continuous TGC has been illustrated in measurement. The fabricated VGA achieves a gain range of 37 dB, a gain error below 1.4 dB, and an input referred noise of 8.6 nV/√Hz for the maximum gain condition.

This letter presents an ultralow noise K-band low-noise amplifier (LNA) using substrate integrated suspended line (SISL) technology. A simplified, purely distributed parameter matching network is utilized for simultaneous noise and impedance matching. Different from standard chip-level circuits, a K-band LNA based on board-level platform with low-cost FR4 is proposed. Using the high-Q value of the SISL platform, this LNA shows the advantages of high-power gain, ultralow noise, and self-packaging. According to the measurement, the proposed LNA achieves a 27.7-dB small signal gain with 2.4-GHz 3-dB bandwidth (25-27.4 GHz) and noise figure (NF) of 1.0 dB with 20-mW power dissipation.

Coherent state quantum communication is attracting extensive attention for its great value in terrestrial and satellite information networks. This paper proposes a new non-orthogonal quantum multi-user (MU) iterative detection scheme. At the receiving end, we develop a composite quantum receiver with multi-stage measurement instrument and soft iterative MU detector. Furthermore, based on a three-dimensional factor graph, a nonlinear Poisson-Gaussian noise limited coherent state iterative MU parallel interference cancellation (PIC) algorithm is derived. Our results demonstrate that this system can well support MU communication and achieve good performance. Quantitatively, for the 8 users scenario, the BER of $10^{-6}$ can be obtained when the photon number is 19. Further numerical results show that the system we designed exhibits superior robustness against imperfections (e.g., quantum mode mismatch and quantum thermal noise).

Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.

A Piecewise Sub-Optimal Threshold (PSOT) is proposed to select the Most Significant Samples (MSS) of the Channel Impulse Response (CIR) for channel estimation of ultrasonic through-metal (UTM) communication. We analyze the correlation of echoes in the UTM channel, i.e., the periodicity and the exponential decay of echoes. The summation of mean-square error (MSE) is partitioned by using the periodicity of the echoes so that each partitioned MSE contains only one echo. The PSOT is derived by setting the first derivative of the partitioned MSE to zero. Channel tap energies, namely the received energies of ultrasonic waves, are required to calculate the PSOT, which can be estimated by using the exponential decay of echoes. After selecting MSSs by PSOT, we propose a further selection approach to get rid of possible noise samples in the MSS by using the correlation of echoes. Simulation results show that the proposed method is robust. Specifically, the performance of the proposed method does not depend on ultrasonic velocity, is unaffected by the estimated number of the echoes at a low signal-to-noise ratio (SNR), and can be applied to UTM channels with different metal thicknesses. The simulation also shows that the proposed method has a lower MSE than other methods, especially at low SNR.

The N-path circuit serves both as a mixer and as a radio frequency (RF) filter. Certain performance aspects, such as noise, linearity, and out-of-band (OOB) rejection dictate large switches size. However, such increment raises the value of the parasitic RF capacitance, which causes further in-band (IB) loss and peak frequency shift. In this brief, we derive simplified equations for the assessment of the mentioned non-ideal properties, using the novel linear periodically time-variant (LPTV) state-space analysis, by making derivations and approximations based on realistic circuit parameters. We present closed-form equations for the voltage gain peak frequency shift and a revised linear time-invariant (LTI) model for the assessment of S11 dip frequency shift.

We introduce a new mode of oscillation in an LC-tank: an inverse class-F₂₃. In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F₃) or/and to the second (in class-F₂/class-F₂₃) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves -95 dBc/Hz and -118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured 1/f³ corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM $_{T}$ ) of -196 and -199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency-phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust operation, the effects of varied data patterns, noise, and channel loss are examined, together with the avoidance of harmonic locking. In addition, a consideration of a sample window is analyzed by fast Fourier transform (FFT) simulation. Fabricated in 40-nm low-power (LP) CMOS technology, the proposed CDR circuit achieves a capture range from 6.4 to 32 Gb/s and a lock time of less than 11 μs. The measured frequency acquisition behavior shows that harmonic locking is avoided with a seamless transition to the fundamental mode. The CDR circuit tested over a 10-dB loss channel achieves a bit error rate (BER) less than 10⁻¹² and energy efficiency of 0.96 pJ/b.

The linearity of high-resolution current-steering digital-to-analog converters (DACs) is often limited by inter-symbol interference (ISI). While dynamic element matching (DEM) can be applied to convert a portion of the ISI to uncorrelated noise instead of nonlinear distortion, DEM alone fails to prevent ISI from at least introducing strong second-order nonlinear distortion. This paper addresses this problem by proposing, analyzing, and experimentally demonstrating a low-cost add-on technique, called ISI scrambling, that, in conjunction with DEM, causes a DAC's ISI to be free of nonlinear distortion. The ISI scrambling technique is demonstrated in a 1-GS/s, 14-bit DEM DAC implemented in 90 nm CMOS technology. The DAC's measured linearity is in line with the state-of-the-art and its measured output power spectra closely match those predicted by this paper's theoretical results.

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5 dB and input return loss (S₁₁)

Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with-2.5 μA $_{{rms}}$ input-referred noise. Optical measurement results at 100 Gb/s show that -8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency.

In this work, the low-frequency noise (LFN) characteristics of hafnium-zirconium oxide (HZO) ferroelectric field-effect transistors (FeFETs) with and without high-pressure forming gas annealing (HPA) treatment are investigated. The origin of 1/f noise in the FeFET without HPA is changed from carrier number fluctuation to Hooge’s mobility fluctuation after wake-up due to the remote phonon scattering from the polarized HZO. Also, Hooge’s parameter is increased by the program/erase (P/E) cycling-induced stress. On the contrary, only the correlated mobility fluctuation is increased after the wake-up in the FeFET with HPA. Furthermore, the LFN of the FeFET with HPA shows robustness to P/E cycling-induced stress after the wake-up, showing superb endurance performance.

Magnetic field shields are important for electronic equipment, ultrahigh-sensitivity sensors, and electrical instruments. For ultrahigh-sensitivity atomic sensors, in particular, ferrite shields with low intrinsic magnetic noise are widely used. In this article, the calculation methods of longitudinal and transverse magnetic noise, which are calculated by loss, are analyzed. The experimental results confirm the feasibility of the model. Using the loss separation method, it is proved that the loss of ferrite magnetic shielding is mainly hysteresis loss, which is below 100 Hz. To effectively reduce the magnetic noise, we analyze the effect of structure parameters on the longitudinal and transverse magnetic noise, and the optimized parameters are obtained. The results show that the longitudinal magnetic noise decreases with the increasing aspect ratio and stabilize eventually. When the aspect ratio exceeds 1, the transverse magnetic noise remains practically unchanged. When the external diameter is fixed, by optimizing the thickness of the magnetic shield, the optimal solution for the longitudinal and transverse magnetic noise is obtained.

Low noise optical amplifiers play a vital role in optical communications and signal processing. Recently, there has been a pursuit for compact, waveguide-based, parametric amplifiers which employ the four-wave mixing process relying on the 3rd order nonlinearity, (3), of the material. Here, we present an analytic model for the gain and noise of phase-sensitive parametric amplifiers based on nonlinear optical waveguides, which includes the impact of the linear loss of the waveguide. We provide insights into the importance of this loss for the gain, but more importantly also for the amplifier noise figure. In particular, we study waveguides based on Si3N4 and find that a gain of 28 dB with a 0.8 dB noise figure is feasible in a 3 m long waveguide having a loss of 1.5 dB/m. We finally investigate the impact of the Si3N4 waveguide cross section on the dispersion and the nonlinear coefficient for the improvement of PSA performance.

The receiver sensitivity is a very important metric in optical communication links operating at low received signal powers. Phase sensitive optical amplifiers (PSAs) can amplify optical signals without excess noise, thus providing a fundamental sensitivity improvement of 3 dB when employed as a pre-amplifier compared to conventional erbium doped fiber amplifiers (EDFA). In this paper, we investigate, both theoretically and experimentally, the sensitivities achieved using power efficient multi-dimensional modulation formats such as M-ary pulse position modulation format (M-PPM) and M-PPM combined with quadrature phase shift keying (QPSK) along with a near-noiseless PSA pre-amplified coherent intradyne receiver. We find that at high signal to noise ratios (SNRs) corresponding to low bit-error-rates (BER), M-PPM+QPSK results in the best sensitivity, which is improved with the order M, while at low SNRs corresponding to high BER (~14% where 100% overhead forward error correction codes (FEC) would be needed to recover the data), QPSK is the most sensitive format, while at the same time providing the best spectral efficiency. We report experimental sensitivities of 2.1 photons per information bit (PPB) at a pre-FEC BER=10-3 using 64-PPM+QPSK and assuming 7% FEC, and 0.8 PPB at a pre-FEC BER= 0.14 using QPSK and assuming 100% FEC.