Search

Au nanoparticle (AuNP)-decorated silicon nanowire (SiNW) field-effect transistors (FETs) were made using a top-down technique to enhance the sensing responses and long-term reliability for the detection of ammonia (NH3). The as-fabricated, diluted hydrofluoric acid (dHF)-treated, and AuNP-decorated SiNW FETs were prepared and characterized at room temperature. These SiNW FETs show better sensitivity and low power consumption in the subthreshold regime than in the linear regime. To evaluate the long-term responses, devices were operated over a period of 120 days. The dHF-treated SiNW FET showed a significant degradation in sensitivity as a function of time, even though it showed the highest sensitivities in the initial stage. The SiNW with AuNPs showed the lowest long-term variation of sensitivity with sufficient linearity. The SiNW with AuNPs showed the lowest drift as low as −0.067%/day for current sensitivity and −0.024%/day for voltage sensitivity, respectively. These results suggest that the deposition of AuNPs on SiNW is very useful for improving the long-term variation in chemical sensing applications.

Highly sensitive silicon-nanonet biologically active field-effect transistors (BioFETs) for the detection of influenza A (H1N1) virus have been demonstrated using a top-down process. The BioFETs show excellent intrinsic electrical characteristics, such as a low threshold voltage of 0.7 V and high on/off current ratio of ~107. The sensing characteristics were measured at room temperature with various concentrations of H1N1 virus in a range of 10 pg/ml - 100 ng/ml. The current-related sensitivity ( ${S}_{ {I}}$ ) shows a higher value in the subthreshold regime, where ${S}_{ {I}}$ is strongly correlated with the subthreshold swing ( SS ). The voltage-related sensitivity ( ${S}_{ {V}}$ ) shows almost constant behavior from the subthreshold regime to the linear regime. The limit of detection (LOD) was 10 pg/ml, which is 6 times lower than values previously reported for FET-type sensors. In addition, the nanonet sensors exhibit high specificity to influenza A virus with negligible false positive for influenza B virus.

The variability due to the displacement damage defect is investigated for various bulk FinFET technology nodes. A random displacement damage from point to clustered defects is introduced by natural terrestrial radiation in arbitrary locations in the silicon channel region. Energy level, position, and size of the defect clusters are considered as variables, and the impact on device performance is investigated for various technology nodes with the aid of the TCAD simulation. It is found that even a displacement defect can cause significant device degradation as the technology node scales down beyond the 10-nm node. Particularly, the abnormal variability may become an issue at sub-6-nm node due to a limited volume of the fin width and the comparable size of the cluster defect.

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling.

A single-event transient (SET) due to alpha particle strike is studied in 11- and 6-nm-bulk FinFETs and 6-nm-bulk nanosheet FET using 3-D TCAD simulation. The nanosheet device shows superior immunity to alpha particles due to the strong gate controllability. The floating nanosheets isolated from the bulk substrate and the surrounding gate structure suppress charging due to ionization radiation. The angular irradiation effect is also studied. The impact of the incident angle is less sensitive on the nanosheet FET compared with the FinFET. This is attributed to the fact that the channel is segmented into three stacks with each controlled by the surrounding gate, thereby physically decoupling the transient charges and reducing the SET in the nanosheet FET.

This letter presents the electrical characteristics of newly proposed network-channel low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs). Due to effective reduction of grain boundary traps and enhanced gate controllability, the network-channel TFTs show better subthreshold slope, lower threshold voltage, and higher ON- OFF current ratio, compared with conventional planar devices. The extracted grain boundary trap density and the interface trap density are significantly reduced in the network-channel devices. In addition, the network-channel devices show higher immunity to hot-carrier stressing, which are confirmed from the low-frequency noise characteristics with various stressing time. These results suggest that the network-channel devices are very promising for next-generation LTPS TFT applications.

Biosensors enable the quantitative detection of target biomolecules in a sample. A biosensor is composed of two parts: the receptor and the transducer. The detection mechanism of biosensors is typically based on a lockand-key approach, also known as the affinity-based approach. A receptor, such as deoxyribonucleic acid or an antibody, captures the target molecules by selectively binding with them for the purpose of detection. The transducer can convert the biobinding event into a measureable signal. For example, a cantilever transduces the mass of biomolecules into a change in resonance frequency, and electrochemical sensors transduce the charge of biomolecules into a change in current. Well-developed transducers are critical for accurate and sensitive detection of biomolecules.

A driving method of pixel circuit using amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is proposed to improve the image quality of active matrix light-emitting diode displays. The proposed pixel circuit employs a diode-connected structure to compensate for variation in threshold voltage ( $V_{\sf {th}}$ ) of the a-IGZO TFT. In addition, the proposed driving method adopts negative bias annealing to suppress the $V_{\sf {th}}$ shift. The annealing time is optimized based on the experimental observation of the minimum $V_{\sf {th}}$ shift. After a stress time of 30000 s, the measurement results show that the $V_{\sf {th}}$ shift is reduced by 29.6%, using an optimized annealing time of 5% of one frame time. In addition, the maximum deviation in the emission current using the proposed driving method was measured to be less than 4.32% after a stress time of 30000 s.

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height ( $H_{\textrm {fin}}$ ) on parasitic resistances and capacitances to achieve the best $RC$ delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The $RC$ delays were directly extracted from the fully calibrated technology computer aided design $I$ – $V/C$ – $V$ simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the $RC$ delay likewise increased due to greater $C_{\textrm {gg}}$ . On the other hand, the $RC$ delay mostly decreased due to greater ON-current as the $H_{\textrm {fin}}$ increased. The $RC$ delay with different power supply voltages ( $V_{\textrm {DD}} = 0.55$ and 0.75 V) was also studied to see the effect of $V_{\textrm {DD}}$ scaling. Finally, a selective deposition was suggested to improve the $RC$ delay about 13%.

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves $RC$ delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based $RC$ calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

In this paper, we proposed the self-assembled monolayer (SAM) as a protection layer against plasma and chemically induced damages to the back interface of an oxide semiconductor during the deposition of the passivation layer. When a thin-film transistor (TFT) is passivated with plasma-enhanced chemical-vapor deposition (PECVD) SiOx and solution-based materials, the back interface of the oxide semiconductor could be exposed to plasma and chemically induced damages, respectively. We employed SAMs on the back surface of the oxide semiconductor prior to the passivation process to suppress such damage. The hydrophobic Cl-SAM (3-chloropropyltriethoxysilane) suppressed the degradation in mobility and subthreshold slope (SS) due to ion bombardment during plasma treatment. The hydrophobic CH3-SAM (octyltriethoxysilane) successfully blocked chemically induced damage due to solution-based passivation.

A new generation of a ubiquitous health smart home is being developed to support the elderly and/or people with chronic diseases in their own home. The goal of the U-Health smart home is to help the elderly to continue to live a more independent life as long as possible in their own home while being monitored and assisted in an unobtrusive manner. This concept of a ubiquitous health care (U-Health) smart home for the elderly has been identified by governments and medical institutions as an important part of the economical, technological, and socially acceptable solution to maintain the health welfare system viable for future generation.

We proposed and fabricated the shift register embedded with a full-swing level shifter employing the depletion-mode In-Ga-Zn-O thin-film transistors (IGZO TFTs). In the level shifter, two clock signals with 180° out of phase and one start signal were employed to obtain a full-swing output. Also, the depletion-mode IGZO TFTs in the shift register were successfully turned off by employing two low-voltage-level signals. The level shifter and the shift register consist of six TFTs and one capacitor, and 11 TFTs, respectively. The depletion-mode IGZO TFT shift register embedded with a level shifter exhibited a high-voltage output pulse without any distortion. The power consumption is 2.13 mW at a VGH of 20 V, a VGL1 of -10 V, and a clock frequency of 12.5 kHz.

In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.

Inorganic materials in the form of thin films are ubiquitous in various applications. In the last two to three decades, the research community and industry have grown thin films of silicon, germanium, III-V compounds, various oxides, nitrides, antimonides, metals, and dielectrics using techniques such as chemical vapor deposition (CVD), metal organic CVD (MOCVD), and molecular beam epitaxy (MBE). These thin films have directly contributed to all the advances we see today in computers, electronics, optoelectronics, and microelectromechanical systems. Some examples include silicon and its oxide and nitride in logic and memory chips, GaAs and AlGaAs in lasers, and tin oxide thin films in chemical sensors. In the nano era, recent efforts have focused on growing all of the aforementioned materials in the form of one-dimensional (1 -D) nanowires.

The series resistance, R sd in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R sd. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R sd values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R sd and the iteration procedure for data fitting is fast and stable.

The effect of a thermal treatment on the exchange field in 19-nm NiFe(bottom)/15-nm FeMn/19-nm CoFe(top) trilayers has been investigated by employing a vibrating sample magnetometer (VSM) and a ferromagnetic resonance (FMR) spectrometer. FMR spectra as a function of applied dc field reveal that there are two distinct resonance peaks corresponding to each ferromagnetic layer. It is found that exchange fields determined from the in-plane angular dependence of the resonance field are in accord with that determined through the magnetic hysteresis loops for the NiFe/FeMn interface rather than the CoFe/FeMn one. A FMR linewidth broadening as a function of the annealing temperatures is attributed to the interdiffusion between the two magnetic interfaces across a FeMn layer.

The conventional source/drain series resistance (Rsd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in Id and there is insufficient physical modeling. In this letter, we propose a modified Rsd extraction method that uses an optimized Id equation and a threshold voltage (Vth) extraction procedure for NWFETs. The Id equation is modified for the geometry of the NWFET, and Vth is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified Id equations to NWFETs. Therefore, Rsd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (dNW) when normalized by dNW, indicating that the extension resistance is the dominant component in the total Rsd.

This paper reports on the development of a novel, compact, low-cost, impulse ground-penetrating radar (GPR) and demonstrate its use for nondestructive evaluation of pavement structures. This GPR consists of an ultrashort-monocycle-pulse transmitter (330 ps), an ultrawide-band (UWB) sampling receiver (0-6 GHz), and two UWB antennas (0.2-20 GHz)-completely designed using microwave-integrated circuits with seamless electrical connections between them. An approximate analysis is used to determine the signal loss and power budget. Performance of this GPR has been verified through the measurements of relative permittivity and thicknesses of various samples, and a good agreement between the experimental and theoretical results has been achieved.

The dc performance and low-frequency (LF) noise behaviors after hot-carrier (HC)-induced stress were compared for a junctionless nanowire transistor (JNT) and an inversion-mode nanowire transistor (INT). Less dc degradation was found in the JNT than in the INT. Due to the low lateral peak electric field (E-field) and electrons traveling through the center of the nanowire, the LF noise increment after HC-induced stress in the JNT is much lower than that in the INT. Furthermore, due to the higher lateral peak E-field located under the gate and the conduction path that occurs near the surface, the LF noise of the INT is very sensitive to HC stress.

The low-frequency noise in the silicon nanowire field-effect transistor (SNWFET) is characterized using SNWFETs with different channel diameters dNW. The current density and the simulation result indicate that the volume inversion as manifested by the spatial charge distribution is enhanced in smaller dNW. The measured noise data are discussed based on the number and correlated mobility fluctuation model. It is shown that the low-frequency noise decreases in smaller dNW. This dNW-dependent noise behavior is clarified in terms of the effective oxide trap density and the fraction of inversion charges near the Si-SiO2 interface.

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.

The hot-carrier (HC) effect in high-k/metal-gate nMOSFETs is characterized using radio-frequency (RF) small-signal parameter analysis. To explain a novel HC degradation of RF small-signal parameters, we propose a modified surface channel resistance model that can be applied to not only conventional SiO2/poly-Si-gate nMOSFETs but also high-k/metal-gate nMOSFETs.

We study quasi-ballistic transport in nanoscale high-κ/metal gate nMOSFETs based on radio-frequency (RF) S-parameter analysis. An RF S-parameter-based simple experimental methodology is used for direct extraction of device parameters (i.e., Leff, Rsd, and Cinv) and the effective carrier velocity veff from the targeted short-channel devices. Furthermore, an analytical top-of-the-barrier model, which self-consistently solves the Schrodinger-Poisson equations, is used to determine the ballistic carrier velocity vinj at the top of the barrier near the source. Based on the results of the experimental extraction and analytical calculations, backscattering coefficient rsat and ballistic ratio BRsat are calculated to assess the degree of the transport ballisticity for nMOSFETs. It is found that conventional high-κ/metal gate nMOSFETs will approach a ballistic limit at an effective gate length Leff of approximately 7 nm.

In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO2 and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO2 bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The model's effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.

Presented in this letter are the C-V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C-V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance Rsd. These observed data are compared with the data from planar MOS capacitor.

This paper presents the development of a new monocycle pulse generator and pulse-to-monocycle-pulse transformer operating in the subnanosecond regime. These circuits employ Schottky diodes, step recovery diodes, and simple charging and discharging circuitry, and are completely fabricated using coplanar waveguides. Simple transient analysis and design of the circuits are presented along with their operating principles. The pulse-to-monocycle-pulse transformer converts a 1 V 300 ps pulse into a 0.7-V 350 ps monocycle pulse. The monocycle pulse generator produces a monocycle pulse having 333 ps pulsewidth and more than 2 V from an input square wave of 10 MHz repetition rate. The generated monocycle pulses have very symmetrical positive and negative portions and low ringing level.

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

We fabricated a thin-film vertical-injection light-emitting diode (LED), which uses a highly efficient coherent external scattering of trapped light by photonic crystal (PhC). The PhC patterns (a = 1200 nm) were formed on top of the n-GaN surface after laser liftoff of the sapphire substrate. This light extraction structure just above micron scale was prepared by a conventional photolithography (lambdac = 405 nm). The Si-gel-encapsulated thin-film LED with PhC patterns (a = 1 200 nm), which had a depth of 500 nm, demonstrated up to 76% improvement in light output power at a forward current of 60 mA, compared with the nonpatterned thin film LED.

Characterized herein are quantum-well Hall devices in Si-delta-doped Al/sub 0.25/Ga/sub 0.75/As/GaAs and pseudomorphic Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As/GaAs heterostructures, grown by low-pressure metal organic chemical vapor deposition method. The Si-delta-doping technique has been applied to quantum-well Hall devices for the first time. As a result high electron mobilities of 8100 cm/sup -2//V/spl middot/s with a sheet electron density of 1.5/spl times/10/sup 12/ cm/sup -2/ in Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As/GaAs structure and of 6000 cm/sup -2//V/spl middot/s with the sheet electron density of 1.2/spl times/10/sup 12/ cm/sup -2/ in Al/sub 0.25/Ga/sub 0.75/As/GaAs structure have been achieved at room temperature, respectively. From Hall devices in Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As structure, the product sensitivity of 420 V/AT with temperature coefficient of -0.015 %/K has been obtained. This temperature characteristic is one of the best result reported. Additionally, a high signal-to-noise ratio corresponding to the minimum detectable magnetic field of 45 nT at 1 kHz and 75 nT at 100 Hz has been attained. These resolutions are among the best reported results.

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.

We report the low-frequency noise characteristics of ultrathin body (UTB) p-channel MOSFETs with molybdenum (Mo) as the gate material. Using the number fluctuation model with correlated mobility fluctuation, the dependence of the noise behavior on bias condition is explained. The impact of nitrogen implantation (for gate work function engineering) on the noise behavior is also presented. An exponential increase in noise with nitrogen implant dose is attributed to interface-trap generation caused by nitrogen penetration through the gate oxide.

We report on the characterization of low-frequency noise in fully depleted (FD) double-gate p-channel FinFETs. While the average noise follows a 1/f dependence, considerable device-to-device variations in noise level are observed due to the statistical fluctuation of the number of oxide traps involved. We found that the low-frequency noise in poly-Si-gated p-FinFETs is mainly governed by the carrier number fluctuation with correlated mobility fluctuation. The low-frequency noise characteristics indicate that the FinFET device can be a promising candidate for analog and RF applications.

Submicrometer MOSFETs with ultrathin oxynitride gate dielectric grown in pure N/sub 2/O ambient were studied. The peak mobility of oxynitride is 5% lower than that of control oxide. However, the oxynitride shows 10% less mobility degradation under high normal field. Compared with the control oxide device, the oxynitride device shows significantly less degradation under channel hot-electron stress. The lifetime of the oxynitride device is approximately one order of magnitude longer than that of the control oxide sample. Significant improvement of device reliability is due to the nitrogen incorporation during the oxidation process. >

Low-pressure chemical vapor deposited (CVD) oxide and thermal oxide of identical thickness (360 A) are compared. CVD oxide exhibits much lower incidence of breakdown at the electric fields below 8 MV/cm, in agreement with the notion that the breakdown is largely due to the incorporation of impurities in the silicon substrate into the oxide during thermal oxidation. Furthermore, CVD oxide shows identical IV characteristics as thermal oxide and significantly lower rates of electron and hole trapping. Based on these results, CVD oxide may be an intriguing candidate for thin dielectric applications.

The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 AA) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 AA/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of >

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.