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Three basic translinear circuit topologies are modified for use at low supply voltage. They are: (1) the balanced translinear loop; (2) the alternating translinear loop; and (3) the instantaneous-companding integrator. The key to this work is the constructive use of nonsaturated MOS transistors operating in weak inversion. This provides two improvements. First, circuit operation is extended to low supply voltage. Second, accurate realization is enabled since the circuits become immune to MOS body-effect. The proposed techniques are suitable for static and dynamic analog signal processing circuits in mixed-signal chips fabricated in digital CMOS technology and operating at the minimum possible supply voltage.

A gain-enhancement technique based on active bootstrapping is proposed which ideally increases the low-frequency gain by two gain stages with no speed penalty and without adding to the phase shift. Therefore, high-frequency performance and feedback stability are not compromised. In practice, the gain enhancement will be limited by nonidealities. The technique is particularly suited for minimum supply voltages since no cascodes are used and, although the discussion pertains to CMOS, can also be applied in bipolar and BiCMOS technologies. A complete analysis, including the effects of nonidealities, is performed. A generally applicable design methodology is formulated.

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method for computer simulation is discussed.

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

The design of integrated, high-frequency, continuous-time filters has made considerable progress in the past few years. As the signal frequencies increase the design of the integrator circuits used in most of these filters becomes more critical. To give direction to the circuit design, minimum specifications for the gain and phase of the integrator circuits would be helpful. A practical method for obtaining these integrator specifications from the filter specifications is developed. The method is applied to a sixth-order Chebyshev band-pass filter, and the result is verified by computer simulation. >

A circuit configuration is presented for wideband analog computation of both the vector-sum function and the RMS-DC conversion function. Design of the circuit is based on a systematic approach to translinear circuit synthesis. Errors due to finite transistor current gain are compensated by means of a novel technique. Measured performance results based on an experimental monolithic implementation in a standard bipolar process are presented. Bandwidths of 25 and 80 MHz are achieved for vector summation and RMS-DC conversion, respectively.

The translinear principle, which is useful in the design of analog integrated circuits, can also be applied to the design of digital integrated circuits. As an example of this technique, a new nonsaturating bistable element is described, which operates according to the translinear principle and which is realizable with standard bipolar integrated circuit processes. The circuit can operate over a wide range of supply current from some milliamperes down to below 1 nA.