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Lead Hafnate-Titanate, Pb(Hf0.3Ti0.7)O3 (PHT), films were fabricated by PLD on Al2O3 (0001) substrates with Pt or SrRuO3 (SRO) bottom electrodes, respectively. There is a certain amount of pyrochlore phase in PHT films on Pt/Al2O3. In contrast, the PHT films on SRO/Al2O3 show pure pervoskite phase. Furthermore, the PHT thin films on SRO/Al2O3, show uniform gain size and significantly enhanced ferroelectric properties with larger remnant polarization (2 Pr = 59.1μC/cm2), better fatigue endurance and lower leakage current density (8.5 × 10−8A/cm2 at 150 kV/cm). With the enhanced properties, PHT ferroelectric film on SRO electrode could be a promising structure which can be applied in FeRAM.

Ferroelectric random access memory (FeRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design due to its high density, high speed operation, anti-radiation and non-volatility. Ferroelectric gate field effect transistors (FeFETs) have been extensively studied and its usage in memory elements and basic analog circuit configurations has gained much interests. Here, we propose a novel architecture of FeFET-based LUT. An improved timing mode of FeRAM chip is analyzed to satisfy the performance of the FeFET-based LUT. Decoder, driver circuit and sensitive amplifier for FeFET array are also proposed. All the simulation results show that the proposed LUT works properly when the frequency reaches 500 MHz at 0.3 V differential input signal.

BiFeO3 (BFO) multifunctional oxide exhibits fascinating multiferroic properties suitable for potential application in nanoscale electronic devices such as non-volatile random accesses memory (FeRAM), field effect transistors, capacitors, logic circuits, etc. In this communication, we report the results of studies on 200 MeV Ag+15 ion irradiation-induced modifications in the structural, microstructural, electrical (I–V, C–V and P–E) and magnetic properties of pulsed laser deposited nanostructured BFO films grown on conducting SrTi0.998O0.002TiO3 (SNTO) substrates. Role of nanoscale structural defects and oxygen vacancies in modifying the physical properties of BFO/SNTO has been discussed in this work.

The ferroelectric transistor (FeFET) provides unique characteristics of memory circuits due to its hysteresis effects. This paper examines the design considerations of a 1T-1C dynamic random-access memory (DRAM) cell using a ferroelectric transistor. The research investigates the effects of the FeFET on the DRAM cell while modifying design parameters which are controlled by the circuit designer. Parameters include channel width and length and write-word-line (WWL) voltage. Experimental data will be taken for different circuit configurations. Comparisons will be made to similar circuits that utilize only metal-oxide-semiconductor field effect transistors (MOSFETs).

Bismuth ferrite thin films with 10% La and 5% Mn (BLFMO) have been deposited using Pulsed laser deposition. It is found that oxygen pressure has pronounced effect on the structural and electrical properties of BLFMO thin films. The leakage current density increases with the oxygen pressure. At 0.007 mbar, the leakage current density is found to be in the order of 10(-7)A/cm(2) at 200kV/cm. The remnant polarization is 73C/cm(2) at 200kV/cm. Fatigue endurance has been studied for optimized film and found that films are almost fatigue free after 10(8) pulses. There is only 3% change in the polarization up to 10(6) seconds as revealed by retention test.

This paper describes an information technology application of FeRAM(ferroelectric random access memory)-based functional memory. A new sorting algorithm is proposed with applications in the field of data processing. The proposed algorithm is evaluated by a simulation program with integrated circuit emphasis (Smart SPICE). Simulation circuits related to the algorithm, that is, the local arithmetic and logic unit, are composed by adiabatic dynamic logic technology. As a result, the proposed algorithm's power delay products are drastically reduced by a factor of 1/300 million when compared to bubble sorting. Even when busline transmission is considered, the power delay products are reduced by a factor of 1/7,000. These impressive results imply that the application of FeRAM in the field of information technology is promising.

Ferroelectric films with three different typical structures, Pb(Zr0.52Ti0.48)O3 (PZT) with Perovskite, SrBi2Ta2O9 (SBT) with layered-Perovskite, and Nd2Ti2O7 (NT) with pseudo-pyrochlore, were prepared on Y2O3 to form a metal-ferroelectric-insulator-semiconductor structure. Our work involves understanding the relationships between retention properties and ferroelectric properties including interface and layer uniformity and insulator layer. NT possessed a relatively larger memory window and better retention property than SBT and PZT. Low permittivity, high coercive field, stable interface, and phase formation without compositional deviation from stoichiometry were found to be the most important control factors for a ferroelectric field effect transistor.

High-k insulator films of HfO2, Y2O3, and CeO2, were prepared on Nd2Ti2O7 (NT) ferroelectric to form metal-ferroelectric-insulator-semiconductor structures. The NT is a candidate ferroelectric material for use in a metal-ferroelectric-insulator-semiconductor field effect transistor (FET) with low permittivity and a high coercive field. Our work involves understanding the relationships between retention property and permittivity and the insulation properties of insulator layer, including interface. HfO2 possesses a relatively low leakage current and a better retention property than Y2O3 and CeO2. The insulating property from a stable interface was found to be the most important controlling factor for the ferroelectric FET.

The proposed UHF Gen2 RFID chip expands its applications to both FFC and NFC through dual field communication scheme with the dual antenna ports. An RF front end circuit with dual field communication antenna ports and the embedded FeRAM technology on the passive UHF Gen2 RFID chip enables the excellent operating performances and the low cost chip for the tag chip applications from the item level to pallet. The metal-ferroelectric-metal (MFM) capacitor, which is the replacement capacitor device for metal-insulator-metal (MIM) or poly-insulator-poly (PIP), is composed of the ferroelectric material as a dielectric insulator. The MFM capacitor is made simultaneously during the FeRAM memory cell process integration without any additional process integration cost. The MFM capacitor of PZT with the thickness of 0.15μm has the high capacitance value of 20–40 fF at unit μm2 area size. The MFM can be stacked over the CMOS layout area, which saves dramatically the capacitor layout area. The MFM capacitor also has th...

Thin films of Lanthanum doped Bismuth Titanate (Bi3.25La0.75Ti3O12) (BLT) have been prepared and characterized for their applications in ferroelectric random access memory (FeRAM) devices. The films have been characterized via X-ray diffraction (XRD), atomic force microscopy (AFM), capacitance-voltage (C-V), ferroelectric (P-E) and current-voltage (J-V) characteristics. The effect of thickness on these characteristics has also been investigated. Thickness variation shows significant effect on the morphology and ferroelectric properties of the films. The nature of the J-V characteristics was observed to be independent of the thickness of the films. Three distinct regions, i.e., ohmic, trap filled limited and Child's law were explicitly observed in J-V characteristics. The J-V behavior of BLT thin films was found to follow the Lampert's theory of space charge limited conduction in an insulator with traps.

(111) oriented PbZr0.52Ti0.48O3 thin films were epitaxially grown on SrRuO3 and SrRuO3/Pt electrode coated Al2O3(0001) substrates by pulsed-laser deposition, respectively. The X-ray diffraction analysis revealed that PZT films on SrRuO3/Pt electrode had better crystal quality than the films on SrRuO3 electrode. Compared to the SrRuO3 electrode, the SrRuO3/Pt hybrid electrode could significantly improve ferroelectric properties of PbZr0.52Ti0.48O3 films with 1 times larger remnant polarization (2Pr = 40.1 μC/cm2), 0.4 times smaller coercive field (2Ec = 40 kV/cm), better fatigue endurance (8.8% degradation at 1011 switching cycles) and lower leakage current density (10−8 A/cm2 at an applied voltage of 5 V). The reliable ferroelectric properties in PbZr0.52Ti0.48O3 films with SrRuO3/Pt hybrid electrode indicate that the combination of the excellent fatigue behavior using SrRuO3 electrodes with the low leakage currents with Pt electrodes can be suitable for the application of integrated ferroelectric devices.

The metal-ferroelectric-semiconductor field effect transistor (MFSFET) was fabricated using polyvinylidene fluoride (PVDF) thin film as a ferroelectric layer. PVDF thin films of 4 and 6 wt% were spin-coated on Si(100) wafers. Ferroelectric hysteretic curves inducing a counterclockwise loop, which means that the deposited PVDF films were crystallized with ferroelectric β phase, was exhibited in the drain current–gate voltage (I D –V G ) characteristics of MFSFET. The memory window widths of the MFSFET were more than 1.6 V. The MFSFET that operates with the PVDF thin film used as a gate dielectric material is shown in the drain current–drain voltage (I D –V D ) characteristics. The MFSFET using PVDF as ferroelectric layer has promising potential for use in low-voltage operable one transistor (1T) type ferroelectric random access memories (FeRAM) using organic material.

The metal-ferroelectric-metal (MFM) capacitor in ferroelectric random access memory (FeRAM) security embedded RFID chip is used not only in the memory cell region but also used in the analog and digital circuit area for low cost capacitance device and high security algorithm. MFM based security FeRAM braces for a wide range of security threats such as reverse engineering, cloning, and tampering. High security performance solution of on-chip FeRAM based register key is implemented to prepare against security attacking. RF transferring sensitivity properties with MFM capacitor are almost same or better than that with poly-insulator-poly (PIP) capacitor and metal-insulator-metal (MIM), and MOS capacitor. The measured power consumption of FeRAM embedded RFID chip without crypto processor engine is about 10μ W with the write sensitivity of -18dBm.

The performance of one and two-dimensional ferroelectric memory capacitors characterized by the hysteresis of applied electric field versus the surface charge density is investigated using the finite element method. Sensitivity of the electrical hysteresis of the 2D capacitor constrained by compliant layers to selected geometrical variables is explored. The remnant polarization and the coercive filed are compared with those of a free-standing film and a film fully constrained by the substrate. The aspect ratio can significantly influence the clamping behavior and thus the remnant polarization of the capacitor.

In this paper, a new paradigm for the operation principle of a ferroelectric random access memory (FeRAM) is presented. The new type of FeRAM is based on piezo–acoustic phenomena in ferroelectric films. It is called Acousto-Ferroelectric RAM (AFeRAM) because its operation is based on the piezo–acoustic method for detecting intrinsic remanent polarization of a ferroelectric memory cell.

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

For a longer working distance between passive tags and the reader, the ferroelectric based technologies are proposed in UHF (860–960 MHz) band transponder. The small ferroelectric capacitor layout area with a stacked capacitor structure over circuit region and a large dielectric permittivity of 250 to 500 and small 1T1C cell array layout area with simple 2T2C based reference scheme allow small chip size. The low operation voltage of 1.5 V to 2.0 V without high voltage boosting scheme also contribute to small power consumption and low cost.

An innovated and the typical one-mask-patterned integrated ferroelectric capacitors process with Sol-Gel deposited technique are investigated. The key improvement for the innovated route is that the ferroelectric film was etched in non-crystalline phase. Due to the etching damage, the ferroelectric and fatigue properties of the typical integrated capacitor were degradation, and the desquamation of top electrode was also existed. The uniformly Pt/PbTiO3/PbZr0.3Ti0.7O3/PbTiO3/Pt (Pt/PT/PZT/PT/Pt) integrated ferroelectric capacitor arrays with explicit and smooth side-wall were obtained by the innovated integrated process. The XRD results exhibit that the innovated integrated ferroelectric capacitor was well crystallized, and the ferroelectric film belongs to the perovskite phase. The etching degradation on the properties of the innovated integrated ferroelectric capacitor was reduced to minimize, confirmed by SEM, EDX results, the ferroelectic and fatigue properties. The innovated process can be co...

A nondestructive readout (NDRO) scheme without polarization reversal in a ferroelectric random access memory (FeRAM) is proposed as a solution for extending the number of readout cycles. However, the readout signal in an NDRO FeRAM is so small that the NDRO operation is sensitive to deformation of the P−V hysteresis loop, which is a manifestation of imprint phenomena. In order to minimize the imprint effect in the NDRO FeRAM, we introduced an asymmetrical polarization programming scheme. Using this scheme, we can expect an extended number of readout cycles more than 1016 regardless of the imprint phenomena in ferroelectric capacitors.

A metal-ferroelectric-insulator-semiconductor structure (MFIS) has been fabricated by ZrO2and Bi3.25La0.75Ti3O12 as the buffer layer and ferroelectric film in forming MFIS diodes on Si(100) substrates, respectively. ZrO2 films were prepared by a sol-gel method. Then, they were carried out dry O2 annealing in a rapid thermal annealing (RTA) furnace at 700°C for 10 min. On the ZrO2/Si structures, Bi3.25La0.75Ti3O12 films were deposited by sol-gel method and they crystallized rapid thermal annealing in O2 atmosphere at 750°C for 30 min. They were characterized by X-ray diffraction analysis (XRD) and atomic force microscopy (AFM). The memory window width in capacitance-voltage(C-V) curve of the Au/BLT/ZrO2/Si diode was about 1.0 V for a voltage sweep of ± 4 V. Base on these results, we fabricated the MFIS-FET structure. The memory window width in drain current–gate voltage (ID–VG) curve of the MFIS-FET was about 0.7 V.

The multilayer PbTiO3/PbZr0.3Ti0.7O3/PbTiO3(PT/PZT/PT) thin films were prepared by a Sol-Gel method on the Pt(111)/Ti/SiO2/Si(100) substrate for FeRAM application. The XRD patterns exhibits a perfect perovskite-phase with strong (111)-preferred orientation. The domain structures were investigated by scanning force microscopy. The out-of-plane polarization (OPP), in-plane polarization (IPP), the OPP amplitude and OPP phase images were obtained. The domain of the films has a complex structure with c-domain and deviated—c-domain which direction deviated from the vertical direction of surface of the film. The complex domain structure is related to the orientation of the crystal grains in the film. The results of ferroelectric, fatigue, dielectric and leakage current density indicate that the thin film has a better property. It has larger saturation polarization P max of 57.6 μ C/cm2 at an applied voltage of 10 V, higher remnant polarization P r of 32.3 μ C/cm2 for a the conceive voltage (Vc) of 2.5 V...

For the integrated ferroelectric memory device, stress of every film in integrated ferroelectric capacitor is an important factor that can influence the properties of ferroelectric capacitor. Stresses of every film in integrated Pt/PZT/Pt capacitor are studied in this work. The PZT film is fabricated by sol-gel method. Al2O3 layer prepared by RF sputtering serves as the Hydrogen barrier interlayer, which presents a little tensile stress. SiO2 layer prepared by RF sputtering is applied to FeRAM as dielectric layer, which generates some compressive stress. The sputtering SiO2 dielectric layer can compensate the influence to ferroelectric capacitors due to tensile stresses from other layers.

One of the problems to be solved to fabricate neodymium substituted bismuth titanate (Bi,Nd)4Ti3O12 (BNT) films by liquid-delivery MOCVD method is that neodymium is hardly deposited into obtained films. In order to increase the deposition amount of neodymium in films, we used Nd(TMOD)3 coordinated with adducts such as 2,2′-bipyridyl (bpy) and 1,10-phenanthrorine (phen) as a neodymium precursor. When the precursor solution including Nd(TMOD)3bpy or Nd(TMOD)3phen was used, the deposition amount of neodymium in films was increased, as compared with the deposition by the precursor solution including Nd(TMOD)3 which was not coincided with target component of BNT film of Bi : Nd : Ti = 3.25 : 0.75 : 3. By optimizing the precursor combination and the mixing ratio, preferentially c-axis oriented BNT films with the target component could be fabricated at the substrate temperature as low as 500°C.

A new 2T/1C ferroelectric memory cell is proposed in this paper. Though the maximal high-density has been sacrificed to some extent, reliable performance with high immunity to data disturbance for good retention has been achieved. Furthermore, larger ferroelectric capacitor area can be available in 2T/1C cell than in conventional 1T/1C cell, which will increase the ferroelectric switchable charge and obtain larger sensing margin.

Metallization properties of TiN/Al/Ti (metal-1) layers deposited by sputtering method were evaluated in a new 16 Mb FeRAM device. The two main features of the device were double W bit-line and Pt/(Bi,La)4Ti3O12/Pt ferroelectric capacitor. The metal-1 films were deposited on both the Pt top electrode and the W bit-line after fabricating the contact holes. The contact filling behaviors of the metal-1 layers were mainly depended on the pre-annealing condition performed before depositing the metal-1 layers. The optimized pre-annealing conditions was 400°C/N2/30 min on W bit-line. From the result, a 16 Mb FeRAM device was successfully developed.

Three dimensional capacitors of Pb(Zr,Ti)O3 [PZT] together with the Ru electrodes were tried to deposit by metal organic chemical vapor deposition for realizing high density ferroelectric random access memory (FeRAM). Good conformability was obtained for both of CVD-Ru and PZT layers on the trenched substrates by optimizing the deposition conditions. In addition, PZT films deposited on Ru bottom electrode showed the good compositional conformability. Finally we demonstrated the Ru/PZT/Ru three dimensional capacitor. These data accelerate the development of three dimensional PZT capacitors.

Distinguished from conventional FeRAM array that has one dimension of bitlines distribution, novel cross bitlines scheme of FeRAM array proposed achieves two dimensions of bitlines distribution and two-dimension access for data in memory array. The drive for memory array can be achieved by more small drivers placed around the memory array in the scheme proposed, which will realize lower total power consumption from all the drivers of memory array. Four cells are accessed at the same time when both a row control-line and a column control-line are activated. The tradeoff among low power consumption, low disturbance to unaccessed cells and high access efficiency can be achieved in the scheme proposed. The scheme can be realized at the device level by multi-level interconnection process and plug structure because of lines placed crosswise, which needs superior fabrication methods and technology.

Reactive Ion Etching (RIE) is used to etch the ferroelectric layer for the ferroelectric random access memories (FeRAMs) research, and the effect of RIE on the ferroelectric properties has been studied. The top platinum layer is etched by Ion Beam Etching (IBE) method, little polarization change has been observed after top electrode etching. The ferroelectric layer is etched by RIE, positive ions bombing the sample during etching and result in the positive ions left in the films. A significant polarization suppression has been found for the capacitors because of large amount ions existed in the films. The polarization can be recovered well after RTP annealing. However, the polarization decreases rapidly during fatigue test, which indicats that the introduced ions have not been removed completely after RTP annealing. On the contrary, the capacitor exhibits better fatigue behaviour because of few ions remained in the film after furnace annealing.

The necessity of producing materials with better performances than those observed in ferroelectric perovskites has induced the investigation of new oxides, especially those belonging to the Aurivillius family which exhibit better performance than PZT in non-volatile ferroelectric memories (FeRAM). In this contribution a Raman analysis of Bi2-xTexSrNb2-xHfxO9 (x = 0.10) is carried out to investigate the vibrational spectra and the ferro-paraelectric phase transition of these compounds.

Pb(Zr,Ti)O 3 (PZT) thin films with Zr/Ti ratio of 50:50 were deposited on Pt/Ti/SiO 2 /Si substrates using the sol-gel method. Since controlling the conditions of heat-treatment is a great role in film growth, post-annealing processes were conducted under different environments. After standard processing, the films were annealed at 600°C under 3 different processes—(a) 30 min in air, (b) 30 min in O 2 ambient and (c) 2 step which was conducted first in air and then in O 2 atmosphere during 30 min respectively. Through electron microscopy and X-ray diffraction, we found that every film was crack-free and highly (111) oriented. Hysteresis measurements showed a generally large polarization value. The fatigue properties differ drastically for every process, showing an abnormal increase near the end of the measurement. The hysteresis loops before and after 1 × 10 10 switching cycles declined for the films annealed under a single-step, but as for the film by the two-step process, the hysteresis showed to increa...

An all-epitaxial stacked ferroelectric capacitor, from the conductive plug to the top electrode, fabricated on a silicon substrate with a metal-oxide-semiconductor field-effect transistor is described. An SrRuO 3 /Pb(Zr,Ti)O 3 /Ir/TiN/Si(100) heteroepitaxial structure with epitaxially grown thin films on a silicon substrate had good crystallinity. Each thin film was oriented in the (100) direction with a cube-on-cube alignment on the silicon crystal lattice. The switching charges of fabricated epitaxial capacitors were around 36 μ C/cm 2 . The charge was less dependent on size for capacitors larger than 5 × 5 μ m.

The ferroelectric behavior of (Bi,La)4Ti3O12 (BLT) films deposited on Si(100) substrates with the use of ZrO2 buffer layers was demonstrated. ZrO2 films were prepared using the sol-gel method. Then, they were subjected to dry O2 annealing in a rapid-thermal-annealing furnace. BLT films were deposited on these structures through the sol-gel method, and they were characterized through X-ray diffraction analysis and atomic-force microscopy. It was found from capacitance-voltage measurements that the BLT films had a hysteresis loop and that the memory window was about 2 V for the voltage sweep of ±5 V. Based on these results, it can be concluded that the use of the BLT/ZrO2/Si(100) structure in the fabrication of MFISFETs (metal-ferroelectric-insulator-semiconductor field-effect transistors) holds great promise.

We report on a novel reference voltage scheme for FRAMs which solves most problems like fatigue, temperature dependency, voltage drop, etc still present in other reference schemes: dynamic reference scheme. It tracks the variations of the ferroelectric capacitors in the memory and provides a common reference voltage line for all sense amplifiers on chip or different reference voltages for different memory banks. No dedicated reference cells are required, instead the memory cells themselves are utilized to generate the reference voltage by periodical test of their voltage levels or by setting a signal that starts the test. This scheme extends life-time and reliability of the memory and enables a self test and repair capability.

A ferroelectric thin film capacitor is the key element in non-volatile ferroelectric Random Access Memories (FeRAM's). There are three important failure-mechanisms influencing the performance of these capacitors: fatigue, retention, and imprint. In this contribution the fatigue and imprint effect are investigated in detail. The material under investigation is lead zirconate titanate (PZT) which was deposited as ferroelectric thin film. Several fatigue measurements were performed with different cycling frequencies, different applied voltage amplitudes, and at varying hysteresis frequencies to investigate dependencies of these parameters on the fatigue effect. An equation is introduced in order to fit the measured behavior of polarization over time and to assign physical parameters to the numerical fitting values. This equation is used to fit the single fatigue curves and the obtained parameters are discussed. Finally, various imprint measurements were performed. Here, the imprint effect was invest...

BLT ((Bi,La) 4 Ti 3 O 12 ) thin films with (117)- and (00l)-preferred orientation were fabricated on Pt/Ti/SiO 2 /Si(100) substrates by a sol-gel method. Films were annealed in O 2 ambient at 750°C for 30 min to crystallize material. In this crystallization process, the temperature heating rate was changed from 0.5°C/sec to 300°C/sec. It was shown from XRD and XRD reciprocal space mappings analyses that the BLT films with (117)-preferred orientation were formed at lower temperature rate, while the films with c-axis preferred orientation were formed at higher heating rate. The remanent polarization (2 P r ) values of the BLT films with (117)- and (00l)-preferred orientation were 36 and 10 μ C/cm 2 , respectively. SEM showed that the (117)-oriented BLT films are composed of peg-like small grains. On the other hand, large platelet-like grains were found in (00l)-oriented BLT films.

The practical use of ferroelectric thin films in devices such as FeRAM requires a capacitance-like geometry and then a bottom electrode. Platinum is proposed based on its resistance to oxidation and unit-cell constants fitting quite closely the ones of typical substrates and ferroelectric materials: indeed, high quality, smooth epitaxial Pt layers with various orientations, namely (100), (110) and (111), were reproducibly obtained. Various examples of the epitaxial regrowth on such sublayers of ferroelectrics are shown, in the case of SrBi2Nb2O9 (SBN) and KTa1− x Nb x O3 (KTN). The observed orientations are compared to the ones obtained on bare bulk oxide substrates and oxide sublayers and discussed in terms of interface anchoring (Near Coincidence Site Lattice model), explaining the orientational competition frequently encountered in such metal-oxide heterostructures.

A description is presented of present efforts to make thin-films for ferroelectric memory devices into truly three-dimensional objects, such as nano-tubes, nano-rods, and nano-ribbons. These may have important applications for DRAM trenched capacitors. A summary of state-of-the-art magnetic RAM (MRAM) and ferroelectric FRAM devices is included.

In order to fabricate highly integrated ferroelectric random access memory (FeRAM), three-dimensional (3D) trench structure should be employed. A capacitor stack, two electrodes and ferroelectric layer, fills the shallow trench. Thus the thickness of each layer is critical to realize 3D structure. It has been well known that that the degradation of ferroelectric layer when it is scaled down is very serious problem. In order to minimize such scaling effect of PZT, the thickness of electrode must be as thin as possible. In this study, we investigated the properties of Pb(Zr,Ti)O3 (PZT) deposited by metal organic chemical vapor deposition (MOCVD) on very thin Ir bottom electrode (40 nm). We found that the Ti film used as glue layer has serious effect on the leakage property of PZT thin film. The leakage problem was reduced by lowering the post annealing temperature.

The fabrication of the FeRAM requires the development of etching processes for ferroelectric thin films and electrodes as well as deposition processes. But different etching methods have different impacts such as resolution and process-induced damages. In this paper, reactive ion etching (RIE) and ion beam etching (IBE) for ferroelectric thin films and Pt electrodes have been studied in details. Different silicon-based ferroelectric thin films and their corresponding electrodes have been etched successfully. To compensate the possible oxygen loss caused by the etching process, the samples should be annealed in O2 at 550°C for 30 min after RIE and IBE etching.

We compared retention characteristics of Pb(Zr,Ti)O3 (PZT) capacitors with either noble metal electrodes or their oxide compounds. Very thin PZT films with thickness below 100 nm were deposited by metal-organic chemical vapor deposition (MOCVD) on Ir bottom electrodes, and Pt, Ir, IrO2 were covered as top electrodes thereon. The capacitors with IrO2 top electrodes had the better opposite-state retention performance than those with Pt, Ir top electrodes. Inserting IrO2 top electrode affected the alleviation of the size effect more in the aged capacitors than in the virgin capacitors. In addition, we also discuss problems of using IrO2 as a bottom electrode in our PZT capacitors.

(Y,Yb)MnO3/Y2O3/Si structure was constructed using alkoxy-derived precursor solutions. The electrical properties of the Y2O3 films were sensitive to deposition condition. The (Y,Yb)MnO3 thin film were synthesized on Y2O3/Si(111) substrates at 750°C in Ar. The quality of Y2O3 films crystallized on Si substrates strongly affect the properties of the Pt/(Y,Yb)MnO3/Y2O3/Si. The properties of Pt/(Y,Yb)MnO3/Y2O3/Si structure could be improved by optimizing the Y2O3 layer. The counterclockwise C-V hysteresis induced by ferroelectric polarization switching was observed. The leakage current densities for the MFIS structure were about 10− 8∼10− 7 A/cm2 at an applied voltage of 5 V. The retention time of the Pt/(Y,Yb)MnO3/Y2O3/Si capacitors was over 104 s.

We discuss in this paper our motivations for implementing the high wafer temperature plasma etching of Ferroelectric films. We present results of our work at high wafer temperature. We present details showing an effective combination of the capabilities of dual frequency plasma etching with high wafer temperature etching in a capacitively coupled plasma reactor. These capabilities allow fine-line geometries to be etched for advanced FeRAM structures. We show an optimized combination of near-vertical profile results with good electrical results.

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μ m CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excell...

We have investigated the imprint characteristics of 100 nm thick-(Bi,La)4Ti3O12, BLT, films prepared both using metal-organic decomposition (MOD) and Sol-Gel spin coating process after the storage for 2 hours to 96 hours at high temperatures of 85°C, 125°C, 150°C, and 175°C, respectively. Reading and writing operation were performed at 25°C and 90°C, respectively. From the results, It was revealed that the imprint characteristics of MOD-BLT and Sol-Gel BLT are almost similar properties.

Recently, La-substituted Bi4Ti3O12 (BLT) has been widely studied as a candidate material for FeRAM due to its superior properties like high fatigue endurance with relatively lower crystallization temperature. In this study, we attempted to examine ferroelectric properties of various BLT thin films that were made using two-step rapid thermal annealing (RTA) process. The microstructure of BLT thin film is appeared as a critical factor to maximize ferroelectric properties. We found that the 2nd annealing temperature in two-step RTA process played an important role in determining the crystalline orientation of BLT thin films. Grain orientations of the BLT thin films were interpreted based on x-ray diffraction (XRD) in conjunction with piezoresponse images that were obtained utilizing piezoresponse force microscope (PFM). In addition, the results were correlated with the hysteresis loops.

Ferroelectric memory devices are under development for future memory technologies due to their ideal properties. They combine non-volatility with fast read/write access, low power consumption and high density making them useful within telecommunication, portable applications and massive data processing. The reliability of the FeRAM device is mainly determined by weak bit cells, which, for some reason, have a smaller cell charge than the average value. The measurement of ferroelectric properties of the capacitors is performed on cell array like capacitor arrays, which give only averaged results for switching charge, coercive voltage and polarization. Therefore these results can not be used to identify single weak capacitors and their location. This inhibits the analysis of the degradation phenomena on a fine scale. The hysteresis measurement on individual cell capacitors overcomes this gap.

In this paper we investigated the thermal stability of a novel CrTiN/TiN double barrier, compared to those of TiN and CrTiN single layer barriers. The CrTiN/TiN double layer was stable against heat treatments at higher than 700°C in oxygen ambient for 30 min. However, the double layer showed a severe Pt and Cr interdiffusion issue after crystallization annealing for PZT. We found that pre-annealing treatments prior to deposition of Pt significantly reduced the interdiffusion. In addition, we also demonstrated ferroelectric characteristics of PZT capacitors on top of Pt/CrTiN/TiO2/Si bottom electrode system for ultra-high density memory applications.

We have investigated the retention characteristics of ferroelectric random access memories (FeRAMs) using a bismuth layered perovskite, (Bi, La)4Ti3O12 (BLT). Due to the charge retention loss in ferroelectric storage capacitors, the sensing signal margin in FeRAM devices decreases from 920 mV at the retention time of 0.01 s to 770 mV at 100 s. From the logarithmic time dependence of the loss of obtained cell signals, the average margin of 520 mV is expected to remain after 10 y at 90°C. In addition, the slower retention loss rate in ferroelectric capacitors in long time retention region, suggests the high device reliability against retention degradation.

A combined method for testing a sol-gel derived strontium bismuth tantalate (SBT) film for non-volatile ferroelectric RAM memories (NVFERAM) that combine fatigue and retention measurements is compared with the conventional one. It results more alike to how a memory cell works in a RAM. Differences between both methods are described and results are discussed on the base of a pining/depining process of domains. A complementary measurement method which based on a programmable logic device has been developed that provides digital responses, to test a ferroelectric capacitor as a single storage cell in a manner close to how a RAM works in a computer, following the measuring strategy of the combined method. Voltage signals are used to write and read information in a small capacitor used as memory cell, evaluating the film before its insertion into the integrated device.

16M 1T1C ferroelectric random access memory was successfully integrated by newly proposed scheme named Recessed Open Barrier (ROB) structure with planar Pt/BLT/Pt/IrOx/Ir stacked capacitor. In conventional barrier metal scheme which bottom electrode was stacked, oxygen diffused through the bottom electrode interface formed during MTP structure integration, and oxidized the edge of barrier metal resulting compressive stress. The failure was accelerated by free oxygen diffusion as the stress built up to make the bottom electrode pop-up. In this paper, the barrier metal TiAlN was recessed and refilled by ALD Al2O3 after bottom electrode patterning. By this novel structure, oxidation resistance was greatly improved, because oxygen diffusion path to BM was much longer than conventional scheme. The contact resistance of storage node was below 10 kΩ/plug after all the thermal budget relevant to BLT capacitor.