Search

The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples. >

A tool capable of synthesizing the symbolic layout of a CMOS cell from its circuit descriptions is presented. The synthesis process is guided by topological constraints on pin and transistor positions, maximum lengths of poly and diffusion wires, and the specification of a preferred layer for each electrical node. The optimization criteria, take into account cell area and aspect ratio, wire length, capacitance to the substrate, and contact and via minimization. The novel placement strategy includes transistor clustering into regions, global region placement by linear ordering, and two-dimensional local transistor placement. The routing combines Steiner trees and Lee algorithms. The program is fast and has been thoroughly tested on small and medium-sized cells. >

Based on mode structure analysis, circuit patterns, and human factors, the authors are building a high speed placement system which follows the practical circuit design procedures for CMOS digital/analog circuits at the transistor level. Built on top of the X window, the system provides a highly automatic, interactive graphics editor with modularity and easily added-on features. The node-based structure enables the system to work on any kind of CMOS circuits and avoids the patterns deadlock problem. In addition, the authors' system also has the advantage of speed. Even with up to 50 transistors, there is no waiting time on the placement display once the netlist is in and the program is executed. The authors also consider the importance of the interface problem at the system level for achieving perfect placement and routing. Transistor placement is part of the automatic schematic design system and runs under a network-transparent, multiprocessing, and multiprogramming environment. The design system allows many users to work on the same chip at different levels on different machines. >

Fast incremental techniques for maintaining and quickly updating the net list underlying a hierarchical schematic design are presented. For most user modifications the net list can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user. As a side result, the incremental net list compiler yields a list of affected electrical nodes that can be used to guide an incremental simulator which resimulates only the affected region of the circuit. >

EXTEST is a knowledge-based program to support the design of testable logic circuits. Starting from a given prototype rule base, a user is able to modify the rule base via a comfortable user interface. Also included is an improved classical testability analysis indicating logical and sequential depth at every node in the network. Topics discussed include knowledge acquisition, rule interface, netlist check, and testability analysis. >

The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices. Cerberus utilizes a general approach to testability rule checking and is part of a computer-aided engineering system to integrate design and test. Cerberus consists of the following components: an extractor to provide a levelized directed graph representation from a circuit netlist, a preprocessor to provide acyclic graphs and for topological sorting of circuit nodes, a rule checker nucleus to perform the DFT verification process hierarchically, and a protocol generator to output the rule-checker results in a user-friendly representation. >

The authors describe a totally deterministic approach and a recursive algorithm for generating device-level schematic diagrams, given only the netlist description of the circuit. The new algorithm is superior to previous tools in that (1) it is deterministic (others use heuristics and therefore cannot handle certain problems), (2) it is fast (others are up to 100 times slower), (3) it is technology-independent (others were written for CMOS only), and (4) it can be implemented in an extremely short program (around 1000 lines of C). >

Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones. >

The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace-tree-based multiplier-accumulators (MACs). MAGGEN generates optimized netlists and compact layouts for MACs. MAGGEN's fast parallel MAC design is achieved through timing optimization routines. Compact layout, on the other hand, is achieved through prudent floorplanning, matched with placement optimization. MAGGEN is an integral tool set. In addition to netlist and layout, it generates all data files to allow the MACS to be used readily as megafunctions (netlist only) or megacells (netlist and layout) in larger designs. >

The authors present a method for transforming multilevel equations into a gate-level netlist of a given technology. The proposed mapping procedure performs multiple mappings, each with randomly selected program parameters. The number of mappings is user-settable, and it offers the designer an option to trade off CPU runtime for better results. This feature is important to designers who begin by exploring the space of architectural possibilities, then finally create a specific, highly optimized circuit. The proposed technology mapping method has been implemented in C as a logic-design tool (McMAP) that takes full advantage of any gate library's timing and area information. Using default parameter settings, the tool synthesized several standard benchmark examples yielding higher-quality circuits with lower CPU requirements than previously reported. >

CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches. >

The author describes a system that automatically generates digital schematics from a netlist description. A combination of algorithmic and heuristic methods are employed to synthetize a schematic as readable as possible. A very special care is given to aesthetic which is a major constraint of that type of software. >

A circuit synthesis program for high-performance small-signal amplifiers, called Ampdes is described. The synthesis can be done with minimal interaction from the user: only the essential information must be given, and the program will produce a Spice net list and a TEX design report. For a typical design, this takes 30 minutes on a mini-computer. Unlike other synthesis programs, it searches in an extremely large set of possible circuits (over 1,000,000 configurations), and is not restricted to one device technology. To ensure a high rate of success in the designs, it uses mathematically sound search rules instead of heuristic ones, and accurate approximations of the circuit behavior. These features require considerable computational effort, and therefore it is necessary to use a refined search strategy to reduce the time for a design run. This strategy is also described. >

The paper presents a comparative study of circuit area and performance degradation among four pipelined RISC processors using different precise interrupt methods. The precise interrupt methods studied in the paper include in-order completion, reorder buffer, history file and future file. The VHDL is used to model five machines at the register transfer level. The Synopsys design compiler is used to synthesise these machines as a netlist of CMOS logic gates, then gate counts are obtained. Based on the model architecture and benchmark programs, it shows that the history file method can achieve the highest performance and consume less silicon area than the reorder buffer method and the future file method.

This paper presents FEHSIM, a novel fault simulator which combines switch-level accuracy (i.e. switch-level fault models) with almost gate-level speed. FEHSIM uses a transistor netlist (e.g. SPICE) to first build the switch level model. In a second step, logic gates are extracted automatically, possibly leaving parts of the circuit such as pass transistors at the switch-level. Both models are kept during simulation. Faults are injected at the switch level. The key innovation in FEHSIM is a so called dynamic scheduler, which decides at run time if the simulation can be performed at gate-level without loosing accuracy. The results show a speed up factor of five compared with 'pure' switch level simulation maintaining full switch-level accuracy. >

This paper describes use of a previously proposed test generation program named Jethro to detect the bridging faults based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects (shorts) in each cell in the standard cell library are analyzed via circuit simulations by monitoring the power supply current. Test sets of each cell are then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test generation program generates the test vectors by trying to satisfy all test sets of all cells in given netlist. The dynamic compaction of the test sets is performed.

A method for the visualization of an analog circuit starting from a netlist is described in this paper. The images obtained have a comprehensible form, symmetrical structures and other analog topological patterns being discovered in the circuit netlist. The method is based on two algorithms. The first one, the symmetry algorithm, exploits the possibility of extracting topology information from a graph representation of the circuit. The second one performs a grid expansion on a directed graph structure, using the results of the symmetry algorithm. The method has been implemented in the "A-warD" program. Test-cases demonstrate the effectiveness of the method.

In a previous work on test generation for I/sub DDQ/ bridging faults in CMOS circuits, a genetic algorithm (GA) based approach targeting the all-pair bridging fault set stored in a compact-list data structure was used. In this paper, we target a reduced fault set, such as the one extracted from circuit layout. The reduced fault set is O(N) versus O(N/sup 2/) for the all-pair set, where N is the number of nodes in the transistor netlist. For test generation purposes, a linear-list data structure is found to be more efficient than the compact-list when a reduced fault list is targeted. We report on results for benchmark circuits that illustrate that test generation using a reduced fault list takes less time and results in more compact I/sub DDQ/ test sets with higher fault coverage of targeted bridging faults. The effects of GA sequence lengths on test generation times and test set quality are also considered.

Rapid prototyping is a well accepted method in microsystems technology. During early design phases a design can be checked against its requirements and, using FPGAs, we are able to easily implement changes and correct faults. The emulation board of the design called MCEMS (Methodology for the design of Embedded Microelectronic Systems), is assembled by FPGAs. To map an application specific embedded controller to this emulation board, the netlist has to be partitioned. None of the existing partitioning strategies are suitable for this system. In this paper we present a hierarchical partitioning approach that satisfies the requirements of this special application.

This paper describes a real-time emulation method based on the use of commercial FPGAs, high-speed interconnect switch devices and software tools (gate array LSI to/from FPGA netlist migration and multi-FPGA partitioning tools) to emulate large scale high-speed communication switching system without the need for conventional specific wiring structures between FPGAs and timing control circuit insertion. This method is applied to line interface units (LUs) that have 20 MHz operation; we employ the LU board and emulation boards, both of which have hierarchical structures with small sub-boards. The proposed LU board structure has the advantage of utilizing a common LU board for rapid prototyping as well as developing cost effective, practical high-performance Asynchronous Transfer Mode (ATM) switching systems for broadband ISDN (Integrated Services Digital Networks). The results of multiple FPGA partitioning on the emulation board suggest that the proposed method will yield economic systems that are also practical.

We present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects in each cell in the standard cell library are extensively analyzed via circuit simulations. Optimal test sequence of each cell is then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test sequence generation (ATSG) program generates the test sequence of the circuit under test by trying to satisfy all test sequences of all cells in the given netlist. The results on ISCAS85 benchmark circuits show that the proposed approach reduces test generation time and test size significantly while providing the capability to adapt to virtually any fault/defect model.

In this paper, we present a module generator which can produce variety of multiplier designs for LUT based FPGAs. It incorporates algorithms for generating sequential, combinational and pipelined designs. The multiplier generator forms a part of the IDEAS synthesis system. Different types of multipliers which can be generated have been included in the IDEAS component library, along with functions which estimate the CLB count and delays for the given size parameters and selected FPGA device. The multiplier generator generates designs for XC3000 and XC4000 family of Xilinx FPGA devices. For Xilinx XC4000 family of devices it takes advantage of the built-in dedicated carry logic to generate fast multipliers. The output of the generator is a netlist in terms of the Xilinx XACT and XBLOX components which is finally mapped onto the FPGA using Xilinx XACT and XBLOX tools.

Existing power estimation tools work on gate-level netlists and cannot be readily adapted for module-level circuits. Flattening the module-level netlist to gate level for purposes of power estimation and subsequent application of a gate-level estimation algorithm are both cumbersome tasks, demanding excessive amounts of CPU time and memory. We present a Module-level Power Estimation tool called MOPE. A preprocessor called PEG (Power Expression Generator) is first used on each module type used in the circuit; PEG compiles signal probability expressions for each output node in the module, as well as an expression for the total power dissipation in the module. These expressions are terms of input signal probabilities, and are stored as part of a module library. MOPE makes use of the signal probabilities of the data inputs and the operational frequencies of modules in conjunction with the power expressions generated by PEG to provide an estimate of the total power dissipation. MOPE can handle both sequential and combinational circuits. We have implemented PEG and MOPE on a Sun SPARC workstation and describe several experimental results which bring out the effectiveness of MOPE as a power estimator.

This paper presents the rapid prototyping process for a communication controller design. It has been specified at a very high abstraction level with no commitment to the final realization architecture. Via VHDL code generation and synthesis a gate level netlist has been generated. For a fast verification of the specification a hardware emulator and a PC have been configured with the design and have been integrated into a real communications network. By this means it has been possible to discover specification failures as fast as possible and to avoid time consuming redesigns.

High level synthesis (HLS) has been mainly concerned with datapath synthesis of a digital system. Consequently, controller effects are often ignored when performing HLS tasks. However, the controller may sometimes have significant contributions to the overall system area and delay. Thus, it is necessary to incorporate the controller effects during HLS. Since control synthesis tools such as MISII are time consuming, it is not feasible to synthesize a controller netlist every time a high level design decision is made. As a result, it is necessary to estimate the controller contribution. As a first step towards a comprehensive prediction scheme, we present a simple yet effective controller estimation model which can be invoked during the register-transfer synthesis phase of HLS, which attempts to reflect the incremental effects of iterative RT level transformations on the controller area and delay. Our model has been bench-marked and found to efficiently account for the controller area and delay. >

There is considerable interest in developing optical interconnects for multi-chip modules (MCM). As a consequence, there is a basic need in developing a methodology for partitioning the system for effective utilization of the optical and electronic technologies. For the given netlist of a system design, key question to be answered is where to use optical interconnections. The authors introduce the computer aided design (CAD) approach for partitioning opto-electronic systems into opto-electronic multichip modules (OE MCM). They first discuss the design tradeoff issues in optoelectronic system design including speed, power dissipation, area and diffraction limits for free space optics. They then define a formulation for OE MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented where improvement for the system packaging has been observed when the partitioning algorithms are applied. >

Describes a complete FPGA-based emulation software system using Virtual Wires technology and present the results of emulating an 18K-gate ASIC implementation of a modified Sparc microprocessor. Virtual Wires overcomes the pin-count limitation that formerly restricted the efficiency of FPGA-based logic emulators. The MIT Virtual Wires softwire compiler accepts a netlist description of the system to be emulated and produces programming information for the FPGA hardware, an inexpensive ($3000) board designed for Virtual Wires in-circuit emulation. The compiler also provides an interface to standard logic simulator tools for hardware accelerated simulation. We discuss innovative features of the compiler system and knowledge gained during its construction. A comparison is made of different implementations of the on-chip Virtual Wires circuitry synthesized by the compiler. Several enhancements to the original Virtual Wires concept are presented that improve the emulation speed and FPGA utilization. >

Summary form only given, as follows. IBM Federal Systems Company, as a prime contractor, has been awarded a $9.5 Million contract by the Advanced Research Projects Agency (ARPA), entitled "Low Volume Access to High Volume Production". The objectives of the contract are the development of a design system that allows customers to enter their design into the IBM Technology Products' Foundry in Hopewell Junction, New York, at various design stages, hybrid chip interconnection technology on a single substrate, participation in the development of industry standards for both known-good-die and the CAD Framework Initiative, and to fabricate, assemble and test multichip modules (MCMs) for use in commercial and military products. The final objective of this contract is to show an order of magnitude reduction in netlist to prototype turn-around-time and non-recurring engineering costs which are consistent with the ARPA ASEM Project goals. >

The author presents a unifying procedure, called three phase cluster partitioning (TPCP), for automated synthesis of a pseudo-exhaustive test generator for built-in self-test (BIST) design. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive testing. A design generator named BISTSYN, based on the TPCP algorithm, was developed and implemented to facilitate the BIST design with this methodology. The input to the design generator can be a circuit description at the gate level which is viewed as a netlist or the circuit output functional dependency sets. BISTSYN provides the BIST mechanisms as the output. The hierarchical design procedure is computationally efficient and produces test generation circuitry with lower hardware overhead and fewer pseudo-exhaustive test patterns than existing techniques. >

The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers. >

A software tool (TOSCA) has been developed which is intended to help non-specialists in the design of systems such as sigma-delta A/D converters and nonlinear oversampled-based signal processors. Time-domain behavioral models were developed for a set of basic building blocks upon which generic circuit structures can be constructed. Very long transients can be simulated in reasonable CPU time, thus allowing the calculation of useful system parameters. The simulator is fully user-friendly in the sense that the circuit description is made by means of a netlist (like SWITCAP) and the results of the distinct possible analysis are stored in text files compatible with standard graphic software tools. Simulation results show the flexibility and the potential of this tool. >

The authors propose a hierarchical gate matrix layout algorithm based on a new net-list. It has remarkable features such that logical equivalence is considered, and the drawback of the greedy method can be overcome by using special features of multiterminal nets. Experimental results for CMOS circuits are far superior to those obtained by another published method. >

A particular instance of system-level synthesis, designing small computers using off-the-shelf components, is discussed. M1 is the synthesis tool in Micon, an integrated collection of tools for rapid prototyping of small computer systems. M1 uses components in a library to build a design that satisfies high-level specifications. Input to M1 consists of requirements on functionality (processor name and speed, amount of memory, and number of serial ports) and constraints (maximum board area and power dissipation). Output from M1 consists of a complete list of parts and a netlist indicating interconnections between the parts. M1 uses a knowledge-based approach to design with a unique architecture that is based on a general and flexible hierarchical design model and supports automated knowledge acquisition. M1 has been successfully used to generate several designs based on four microprocessor families; knowledge of these designs was acquired by an automated knowledge acquisition tool. >

A partitioning technique is presented of functional models that are used in conjunction with high-level synthesis of digital synchronous circuits. The partitioning goal is to synthesize multi-chip systems from one behavioral description that satisfy both chip area constraints and an overall latency timing constraint. There are three major advantages to using partitioning techniques at the functional abstraction level. First, scheduling techniques can be applied concurrently to partitioning. Therefore, partitioning under timing constraints, and in particular under latency constraints, can be performed. Second, the functional model captures large hardware systems with fewer objects (than at the logic netlist abstraction level), making the partitioning algorithm more efficient. Third, hardware sharing tradeoffs can be considered. Hardware partitioning is formulated as a hypergraph partitioning problem. Algorithms for hardware partitioning are presented and experimental results are reported. >

An edge-based netlist extractor using a relocatable netlist representation scheme is described. Retaining an existing layout hierarchy, it extracts the devices formed as a result of cell overlaps. Using the implemented overlap-handling algorithm, it is possible to access cell pins not available at the boundary of the cell. The extractor handles all angled geometrics. Total volume of data handled by the extractor is reduced by extracting a cell netlist only only and modifying this netlist according to the nature of the cell instance overlap. The extractor is implemented in C under a Unix environment. >

A hierarchical search software package that allows an application to retrieve flattened netlist data from a hierarchical netlist database. An algorithm is presented that implicitly searches the entire VLSI CAD net list data space without first constructing it. While traditional methods construct the entire search space explicitly, which helps to achieve a fast O(1) query time but requires Omega (n) space, this method relies on the circuit hierarchy to prune the search effectively. It is shown that the hierarchical net list data space is smaller by a factor of O(n/sup epsilon /). Where O >

This paper presents an approach for using the Verilog Hardware Description Language (HDL) together with artificial intelligence (AI) concepts such as genetic algorithms and neural networks in a next generation diagnostic automatic test pattern generation (ATPG) system. The test generation portion of the system is composed of four basic functional elements: optimizing test proposer, simulator, unsupervised pattern classifier and evaluator. The test proposer and the evaluator are implemented using a genetic algorithm (GA). The unsupervised pattern classifier is implemented with an adaptive resonance theory (ART) neural network. The model development portion of the system is composed of three basic functional elements: netlist generator (NG), component model library (CML) and automatic model builder (AMB). The paper addresses the use of the Verilog HDL in the netlist generator, automatic model builder, component model library and simulator functions. A circuit model development process is described which allows for the creation of the good circuit model as well as the fault models necessary as part of the ATPG system.

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.

This paper describes the floorplanning for FPGA based designs. In order to perform placement for very large designs, the currently followed approach of placing flat netlists is extremely time consuming. Also, managing large data sets, as in flat netlist files, is not trivial for performance driven designs. In this paper we describe an approach for the constraint-based FPGA floorplanning of flexible and fixed macro blocks. Our approach is to construct a floorplan of small area that respects the input constraint set. The input constraint set is derived from topological placement of the macro blocks based on both FPGA architectural constraints and ASIC design. Experimental results on FPGA floorplanning are also presented for large benchmark examples.

Testing of embedded cores poses a great challenge. These cores cannot be tested in isolation because core I/Os are not directly accessible from ASIC I/Os. A novel test methodology is developed which generates a partial netlist for protection of intellectual property (IP) by performing structural analysis. This partial netlist is used in ASIC level test generation. For the remaining gates of the core, patterns are supplied to test those gates, which can be applied through only core scan chain. Another scheme is developed to select a few I/Os optimally to add boundary scan circuits to improve IP protection.

In the spectral method, the vertices in a graph can be mapped into the vectors in d-dimensional space, thus the vectors are partitioned instead of vertices to obtain graph partitioning. In this paper, we show a method to obtain optimal two-way vector partitioning based on an optimal direction vector. As the problem to find the optimal direction vector is NP-problem, we propose an efficient heuristic to obtain high quality direction vector. As we approximate a given netlist into the graph and only use ten eigenvectors in practice, there is a chance to improve the solution quality by local optimization. Fiduccia-Mattheyses algorithm is employed as a post processing. Compared with FM and MELO, the proposed algorithm PDV reduces cutsize on the average 40% and 20.5%, respectively.

With the widespread adoption of top-down design methodologies using HDL and synthesis, RTL models have become the "golden" design database. However, ASIC and FPGA vendors still require a gate level netlist as the official sign-off design. Model ambiguities in RTL designs can cause differences between RTL and synthesized netlist designs. These differences in the best case cause simulation mismatches between RTL and gate designs. In the worst case, if not detected in simulation they can result in faulty hardware. This paper covers common sources of ambiguity in RTL models. Solutions are provided for avoiding these situations. Some basic simulation debug tips are provided to help identify these errors in simulation with both VHDL and Verilog. These examples are based on Synergy (Cadence's synthesis tool) but also apply to synthesis in general.

We describe a time and space efficient technique for evaluating the SCOAP testability measure of a circuit from its hierarchical description. Under the stuck at fault model, the SCOAP measure introduced by Goldstein is known to offer a good estimate of the controllability and observability of a given circuit. SCOAP works on a gate-level netlist, and can be expensive in terms of memory and computational resources when large circuits of VLSI complexity are involved. We show that this problem can be alleviated by taking advantage of a hierarchical representation of the circuit. We introduce the notion of SCOAP expression diagrams for functional modules, which can be precomputed and stored as part of the module database. The hierarchical testability analysis program, HISCOAP reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measures in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential.

This paper evaluates the feasibility of reconfiguring an FPGA at run time, and tests its performance using a "Grand Challenge Problem", the high speed scanning of genomic sequence databases. Algorithm implementation into a XC3090 FPGA is described, and methods proposed for generating a placed Xilinx Netlist File that can be efficiently routed at run time by the Automated Placing and Routing Xilinx tools, in order to increase the speed and the density of the design. The same algorithm carefully optimised on a RISC processor has been compared with the run time reconfigurated FPGA, and shows the latter to have an improvement in speed of two to three orders of magnitude.

This paper demonstrates a method to allow rapid design from a high level VHDL program down to a simple netlist. Each stage of the design process generates a complete design representation as the behavioral axis of the Y-chart is descended. These design representations can be simulated to verify operation at each stage. The result is a fast and efficient method for digital design. >

We present a recursive method for generating layout for VLSI chips based on integrating layout directives in the netlist description. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense BiCMOS VLSI microprocessor chips automatically.

An encapsulated writing style of Verilog is described together with models for a corresponding scheduler and synthesizer. The method provides a middle ground between synthesis from behavioral specifications, which implies decisions too difficult for architectural synthesis, and synthesis from pure structural specifications, which necessitates providing full details of the controller and netlist. The input writing style is designed to be as concise as possible. This is done by the encapsulation of the functionality of major submodules, and implicit (inferred) control. In this way it is possible to describe complex functional architectures in an economical and transparent manner. This description can be transformed semi-automatically by steps through intermediate styles and eventually to a pure structural specification containing fall details of timing invocations and interconnections to appropriate controllers. At each stage after the first, the writing styles can be fully accessible to native Verilog simulators. The efficiency and economy of this style is demonstrated by a simulation of the well known DLX processor benchmark with full pipeline bypasses.

A synthesis-based approach to improving the testability of digital filters is presented, with the aim of producing designs that achieve very high fault coverage under low-overhead built-in self-test methodologies. The synthesis-based approach permits high coverages to be achieved without the addition of special test hardware or other manipulation of the gate-level netlist. The testability of a design is enhanced at the register-transfer level (RTL), prior to synthesis. Using scaling as a redundancy elimination technique, it is possible to reduce the area required by a design, as well as identify further redundancies that can be eliminated through the automatic selection of optimized RTL structures drawn from a parameterized VHDL library.

In this paper, we firstly propose a k-way connection-oriented net model, chain net model, to generalize the cut analysis for k-way circuit partitioning and to reduce the complexity of edges for the representation of a multiple-pin net between the transformation of a hypergraph and an edge-weighted graph. Furthermore, based on the techniques of fuzzy c-means clustering, we develop and propose fuzzy c-means graph clustering to obtain k groups of fuzzy memberships for the vertices in the mapped graph according to the global information of all the net connections. Finally, by the area information of any cell in the circuit netlist, these k groups of fuzzy memberships will lead to a cut-driven or balance-driven k-way circuit partitioning. As a result, k-way circuit partitioning has been implemented for testing MCNC circuit benchmarks and the experimental results show that the proposed partitioning approach generates effective results on the partitioning cut and the partitioning balance for these benchmarks.

This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimize the implementation. Our procedure begins with a timed specification and a delay-annotated gate library description which must include 2-input AND gates, OR gates, and C-elements, but optionally can include higher-fanin gates, AND-OR-INVERT blocks, and generalized C-elements. Our procedure first generates a technology-independent timed circuit netlist composed of possibly high-fanin AND gates, OR gates, and 2-input C-elements. The procedure then investigates simultaneous decompositions of all high-fanin gates by adding state variables to the the specification and performing resynthesis. Although multiple decompositions are explored timing information is utilized to significantly reduce their number. Once all gates are sufficiently decomposed, the netlist can be mapped to the given gate library, taking advantage of any compact complex gates available. The decomposition and resynthesis steps have been fully automated within the synthesis tool ATACS and we present results for several examples.