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CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis
- Source :
- ICCAD
- Publication Year :
- 2003
- Publisher :
- IEEE Comput. Soc. Press, 2003.
-
Abstract
- CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches. >
Details
- Database :
- OpenAIRE
- Journal :
- [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
- Accession number :
- edsair.doi...........0f37092277e7ac9f9e733d36a8fce5d4