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An enhanced delay test generation procedure for high-speed logic LSIs is presented. The procedure is applicable to general scan-designed sequential circuits including both level-type flip-flops and edge-type flip-flops. Some techniques are introduced to solve the problem of 'same-clock signal transfer' between these flip-flops and to enhance the performance of the delay test generation procedure. The effectiveness of the procedure is demonstrated by the experimental results obtained. >

The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit. >

This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic approach is effective for solving test generation problem. >

This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach.

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach.