A parallel sequential test generation system DESCARTES based on real-valued logic simulation

Authors :: H. Date
M. Nakao
K. Hatayama
Source :: Asian Test Symposium
Publication Year :: 2002
Publisher :: IEEE Comput. Soc. Press, 2002.
Abstract: This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach.

Subjects :: Very-large-scale integration
Sequential logic
Computer architecture
Computer science
Design for testing
Parallel algorithm
Redundancy (engineering)
Logic simulation
System testing
Parallel computing
Automatic test pattern generation

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