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In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top-down fabrication approach, we demonstrate a 9-nm diameter VNW TFET with excellent on-state characteristics featuring a peak transconductance of 90 $\mu \text{S}/\mu \text{m}$ at $V_{{\text {ds}}} = -0.3$ V. The same device exhibits a minimum linear subthreshold swing of 225 mV/dec at $V_{\text {ds}} = -0.05$ V. Our p-type GaSb/InAsSb TFETs exhibit clear negative differential resistance at room temperature, with a peak-to-valley current ratio over 3. The excellent device performance of these devices bodes well for the viability of GaSb-based complementary TFETs in future ultra-scaled logic technologies. [ABSTRACT FROM AUTHOR]

The nucleation-limited switching (NLS) model has been shown in the literature to explain successfully the dynamics of polarization switching of polycrystalline ferroelectric films (FE) in various experiments. However, because of its mathematical complexity, the NLS model has yet to be implemented correctly and efficiently in the simulation of actual, experimental circuits with complex driving waveforms. Here, we reformulate NLS as a generalized polarization rate equation that captures correctly the incubation time of nucleation and the intra- and inter-grain switching statistics of kinetics without any restrictions on waveform and switching time scales. This formulation forms the basis for efficient numerical finite-difference computation, which is verified in realistic circuit simulations of a number of experiments. [ABSTRACT FROM AUTHOR]

We present a novel test structure for the study of sidewall ohmic contacts to III–V fins for FinFETs. We apply it to the characterization of the impact of digital etch (DE), used to trim the fin width, and thermal annealing on the contact resistivity of Mo/ $\text{n}^{+}$ -InGaAs fin sidewall contacts. To obtain sidewall contacts, we leave in place the etch mask that is used to define the fins in a reactive ion etching process and deposit conformal Mo around them. We present a model that describes well the electrical characteristics of the test structure. In our results, we find that the specific acid that is used for DE or the number of DE cycles that are performed have a minor impact on contact resistivity. Thermal annealing is found to significantly improve the sidewall contact resistivity, with the best value of $3.7~ \pm ~0.2~ {\Omega } \cdot {\mu } \text{m}^{{2}}$ obtained after annealing at 400 °C. This is about three times higher than the reported contact resistivity for this contact technology with the contact wrapping around the top and the sidewall surfaces of fins, about $1.3~ {\Omega } \cdot {\mu }\text{m}^{{2}}$. Also, we find that the width of the non-conductive region under the sidewall surface of Mo contact, which we term “deadzone,” can be significantly mitigated by thermal annealing. Our work highlights the importance of understanding sidewall ohmic contact formation for future high-performance InGaAs FinFETs. [ABSTRACT FROM AUTHOR]

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on I – V/C – V measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using I – V/C – V. To address this issue, we demonstrate a new mobility extraction technique (RF- ID) based on concurrent I – V and S-parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/V⋅s is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel. [ABSTRACT FROM AUTHOR]

GaN electronics constitutes a revolutionary technology with power handling capabilities that amply exceed those of Si and other semiconductors in many applications. RF, microwave, and millimeter-wave GaN-based power amplifiers are now deployed in commercial communications, radar, and sensing systems. GaN power transistors for electrical power management are also starting to reach the marketplace. From the dawn of this technology, inadequate transistor stability and reliability have represented stumbling blocks preventing widespread commercial use of GaN electronics. Intense research has been devoted to addressing these issues, and great progress has taken place recently. This article reviews some of the most interesting and significant stability and reliability issues that have plagued GaN power field-effect transistors for RF and power management applications. [ABSTRACT FROM AUTHOR]

In this article, a detailed simulation study of high-performance InGaAs quantum-well (QW) MOSFETs is presented. We demonstrate that the limited free carrier density in the access region leads to a significant source starvation effect in the saturation regime, which limits the maximum transconductance (${g}_{m}$). By coupling ballistic 2-D quantum mechanical simulations with an original semiclassical model for source starvation, we are able to reproduce quantitatively the ${V}_{\text {GS}}$ – ${g}_{m}$ characteristics of three successive device generations differing only in the design of their access region. Source starvation is approximated as a quasi-equilibrium phenomenon characterized by a nonlinear, current-dependent voltage drop in the access region that reduces injection into the channel at high currents. Even in the most recent record device with a ${g}_{m}$ peak of 3.45 mS/ $\mu \text{m}$ , source starvation is found to have a negative impact. An extrapolation of our model furthermore suggests that source starvation will become a major performance bottleneck in future device realizations with lower trap densities. [ABSTRACT FROM AUTHOR]

We study the impact of fin-width scaling on transport in highly doped InGaAs fins and the effect of digital etch (DE). Our experiments suggest the existence of a 10-nm-wide “deadzone” on each side of the fin that does not contribute to the transport. The extent of the deadzone cannot be mitigated by DE nor sidewall passivation. Simulations suggest that the Fermi-level pinning and its associated subsurface depletion region alone cannot explain the relatively wide deadzone that is measured. We propose an explanation based on the combination of Fermi-level pinning and mobility degradation as the fin width scales down. This leads to an apparent wider deadzone than accounted by the Fermi-level pinning alone. [ABSTRACT FROM AUTHOR]

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length. [ABSTRACT FROM AUTHOR]

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain. [ABSTRACT FROM AUTHOR]

A p-type Diamond:H/WO3 metal–oxide–semiconductor field-effect transistor (MOSFET) based on surface transfer doping is demonstrated. Using a low-temperature ALD-grown HfO2 as gate insulator, the Diamond:H/WO3 MOSFETs show excellent output characteristics, gate-controllable 2-D hole gas, and low gate leakage current. Long-channel FETs exhibit improved subthreshold behavior but reduced transconductance with respect to short-channel devices. An observed WO3-thickness-dependent threshold voltage is consistent with enhanced surface transfer doping as the WO3 layer is thinned down. Low-temperature measurements suggest a significantly lower mobility than expected in this material system. This illustrates the challenge of maintaining high TMO quality during device fabrication. [ABSTRACT FROM AUTHOR]

We present a detailed study of the off-state leakage current in scaled self-aligned InGaAs FinFETs. In long-channel devices, band-to-band tunneling at the drain-end of the channel is shown to be the root cause of excessive off-state current. This conclusion emerges from its characteristic electric field and temperature behavior and the absence of gate length and fin width dependencies. In short-channel devices, off-state current is significantly larger and it increases as the gate length shortens or the fin widens. We attribute this behavior to current multiplication through the gain of a floating-base parasitic bipolar transistor that is present inside the MOSFET. We extract the bipolar current gain which in short-channel devices is found to increase as the gate length shortens and decrease as the fin width narrows. In long channel devices, the current gain drops exponentially due to base recombination. This has allowed us to extract the diffusion length of electrons in the body of the transistor. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal–dielectric interfaces, and enhanced electron–hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions. [ABSTRACT FROM PUBLISHER]

The electrical degradation of InAlN/GaN high-electron-mobility transistors for millimeter-wave applications has been examined under simultaneous high VDS,stress and high IDstress electrical stress. Besides a drain current decrease and a positive threshold voltage shift, the creation of an anomalous source-side gate leakage path has been identified. We attribute this to high electric-field induced trap generation in the AlN layer directly under the gate edge on the source side. The resulting increase in gate leakage further exacerbates the degradation of the gate diode. In addition, we postulate that high-power stress leads to significant device self-heating that causes gate sinking and leads to a permanent positive threshold voltage shift and drain current degradation. [ABSTRACT FROM AUTHOR]

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates. [ABSTRACT FROM PUBLISHER]

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current. [ABSTRACT FROM PUBLISHER]

This letter demonstrates top-down InGaAs/ InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at \textV\mathrm {ds} = 0.3 V has been obtained at room temperature. An I60 (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/ \mu \textm has been achieved at \textV\mathrm {ds} = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthresholdcharacteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide–semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment. [ABSTRACT FROM AUTHOR]

Physics-based transistor models are important for technology projections and circuit simulations. To date, there has been little discussion on the incorporation of ballistic effects in transistor models. Recent experimental studies have revealed the significance of ballistic transport in the electrical characteristics of nanometer-scale InGaAs MOSFETs with ultra-low external resistance. Without proper accounting for the ballistic resistance and its gate voltage dependence, the access resistance to the intrinsic device cannot be accurately determined, and any physics-based transistor modeling is bound to fail. In this letter, we show that the MIT Virtual Source model, which natively captures ballistic transport physics, correctly incorporates the impact of ballistic resistance. As a result, it accurately models the electrical characteristics of self-aligned nanoscale InGaAs MOSFETs, an excellent model system for near-ballistic transistors, over a broad operational range. We also show that the success of the model development effort crucially relies on the correct extraction of the external source and drain resistance, R{\text {sd}} , from experimental measurements. [ABSTRACT FROM AUTHOR]

We present a comprehensive study of bias temperature instability (BTI) in GaN MOSFETs under moderate positive and negative gate bias stress. We investigate the evolution of threshold voltage ( V_T) , maximum transconductance ( gm,max) , and subthreshold swing (S). Our results show a universal continuous, symmetrical, and reversible V_T shift and gm, max change as gate stress voltage ( \text V{{\text {GS,\text {stress}}}}) increases from −5 to 5V at room temperature. The time evolution of V_T is well described by a power law model. The voltage dependence, time dependence, and temperature dependence of our results suggest that for moderate gate bias stress, positive BTI and negative BTI are due to a single reversible mechanism. This is electron trapping/detrapping in preexisting oxide traps that form a defect band very close to the GaN/oxide interface and extend in energy beyond the conduction band edge of GaN and below the Fermi level at the channel surface at 0 V. [ABSTRACT FROM PUBLISHER]

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work. [ABSTRACT FROM PUBLISHER]

This letter introduces a novel alcohol-based digital etch technique for III–V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V \mathrm { {DS}}= 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides. [ABSTRACT FROM AUTHOR]

This paper is aimed to compare the performance of toroidal inductors and planar spiral inductors in multilayered technologies, in terms of achievable inductance density. The optimization of planar toroidal inductors in multilayered substrates is investigated theoretically, and closed formulae are derived for their inductances as a function of geometrical parameters. The obtained model is validated by experimental results and electromagnetic simulation. From the comparison of the inductance of toroidal inductors and compact spiral inductors, a selection rule is proposed to choose the most suitable topology that leads to the most compact design. [ABSTRACT FROM AUTHOR]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]