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A novel 3D NOR memory array with single-crystal silicon channel, high-density and fast-read was proposed and fabricated. The proposed 3D NOR memory is investigated in terms of device structure, integration scheme, and circuit architecture. To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices, and 3) unlike 3D NAND, bit-line planes, source-line planes and vertical word-lines were utilized. Due to the use of single-crystal silicon channels, our memory devices have large read currents of $110 ~\mu \text{A}/\mu \text{m}$. Through programming/erasing tests, the programming speed of $10 ~\mu \text{s}$ and erasing speed of 100 ms were obtained, which are comparable to that of the 2D NOR Flash with single-crystal silicon channels. [ABSTRACT FROM AUTHOR]

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high-k metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed. [ABSTRACT FROM AUTHOR]

Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high- $\kappa $ metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained. [ABSTRACT FROM AUTHOR]

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NMM) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization (Pr) and coercive electric (EC) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states. [ABSTRACT FROM AUTHOR]

The impact of As preamorphization implant (PAI) on specific contact resistivity (ρc) is investigated for Ti-based Ohmic contacts on n+-Si in this article. The ρc value of TiSix/n+ −Si contacts is greatly improved with low-dose As PAI whereas this improvement is impaired with increased dose of As PAI. The ρc results from the joint effort of the reduction of effective Schottky barrier height (SBH) to electrons (φbn,eff) , retardation of Ti silicidation, and annihilation of end-of-range (EOR) defects. Besides, the interfacial microstructures of TiSix/n+ −Si affect ρc, correlated with the post metal anneal (PMA). [ABSTRACT FROM AUTHOR]

A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work. [ABSTRACT FROM AUTHOR]

High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high- ${\kappa }$ metal gate FinFETs fabrication flow. The devices show improved subthreshold swing values [34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices] and slight hysteresis voltages (~9 mV for $\textsf {L}_{\textsf {G}} = \textsf {500}$ nm and ~40 mV for $\textsf {L}_{\textsf {G}} = \textsf {20}$ -nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low-interface state density (${D}_{\sf it}$) and the perfect channel electrostatic integrity. [ABSTRACT FROM AUTHOR]

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high- k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low V_{T} . Compared with halo doping with the same V_{{T,{\rm sat}}} at VDD = 0.8 V, despite no I\mathrm{{\scriptscriptstyle ON}} enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same I\mathrm{{\scriptscriptstyle OFF}} = 100 nA/ \mu \textm at V_{\rm DD} = 0.8 V, the SPW structure reduces DIBL by 16%, enhances I\mathrm{{\scriptscriptstyle ON}} by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping. [ABSTRACT FROM AUTHOR]

Cloud manufacturing (CMfg) is an emerging paradigm that aims to provide on-demand manufacturing services over the Internet. Service composition as an important means for generating value-added services plays an important role in achieving the aim of CMfg. Most of previous works focused on exploring techniques of service composition for a single composite task using meta-heuristic algorithms. However, the issue of service composition for multiple composite tasks has rarely been considered. Meta-heuristic algorithms suffer from cumbersome parameter tuning as well as the tendency of getting into local optima. In addition, the effectiveness of different algorithms has not yet been fully explored when different degrees of constraints are imposed. Different from approaches in most of the previous works, this paper proposes an extended Gale–Shapley (GS) algorithm-based approach for service composition that allows generation of multiple service composition solutions effectively. Requirements with different constraints are considered. Experimental results indicate that: 1) meta-heuristic algorithms can be used in various scenarios with different degrees of constraints. However, they are incapable of finding the optimal solutions in situations with relatively loose constraints, and moreover, the failure rate of finding solutions for a batch of multiple tasks is high; 2) the dynamic programming (DP) is a method that is the most sensitive to constraints. It performs better only under loose constraints and in the case of a single requirement; and 3) the application range of the GS method proposed is wider than that of the DP method. It can achieve better performance when constraints are relaxed irrespective of task status (i.e., a single task or multiple tasks), and moreover, it can make more tasks find solutions in the multitask scenario without service reuse. [ABSTRACT FROM AUTHOR]