Search

The leakage current degradation, single-event burnout (SEB), and single-event gate rupture (SEGR) behaviors induced by the heavy-ion irradiation in p-Channel and n-Channel power U-shaped metal–oxide–semiconductor field-effect transistors (UMOSFETs) are comparatively investigated in this article via experiments and simulations. The SEB and SEGR performances of a commercially available −100-V-rated p-Channel UMOSFET are tested under heavy-ion irradiation. The experimental results show that the sample devices can be prevented from the drain leakage current or gate leakage current degradation under the bias conditions of $V_{\mathrm {GS}} = -100$ V and $V_{\mathrm {GS}} = 0$. However, a severe gate leakage current degradation can occur at $V_{\mathrm {DS}} = -100$ V when $V_{\mathrm {GS}} \ge 5$ V. In addition, the SEB and SEGR characteristics of a 100-V-rated n-Channel UMOSFET are obtained by simulations. The simulation results indicate that a p-Channel UMOSFET can achieve much better robustness against heavy ions compared with an n-Channel UMOSFET. Further, the leakage current degradation and failure mechanisms induced by heavy-ion irradiation are investigated via simulations. Finally, an effective method, which enlarges the width and depth of the source contact trench, is introduced to enhance the SEB tolerance of an n-Channel UMOSFET. The simulation result shows that the SEB threshold voltage can represent an increase of 23.1% with the hardening method. [ABSTRACT FROM AUTHOR]

In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations. [ABSTRACT FROM AUTHOR]

This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction (SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS (C-VDMOS), which indicated a severe degeneration threshold of 500 V. The SiC common SJ VDMOS (C-SJ VDMOS) was proven to be sensitive to high-energy heavy-ion and represents comparative SEB performance compared with the SiC C-VDMOS. The robustness of the SiC SJ VDMOS with different single buffer layer (SBL) designs against a heavy-ion was simulated. It is found that the maximum temperature in the source metal/SiC interface and bottom of the structure could be compromised by the thickness of the buffer layer. As a result, the SiC SJ VDMOS with an optimal SBL exhibited a severe degeneration threshold of 800 V, which was a 60% increase compared to the SiC C-SJ VDMOS. [ABSTRACT FROM AUTHOR]

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ($R_{ {on,sp}}$) of the SOI BP-LDMOS is 9.5 $\text{m}\Omega \cdot {\mathrm{ cm}}^{{2}}$ with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm2. The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si). [ABSTRACT FROM AUTHOR]

This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power metal–oxide–semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion’s strike position to SEB is proved to be the edge of the P+/P− JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure’s 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one. [ABSTRACT FROM AUTHOR]

In this article, a novel snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P+ pillars at the collector side (PPC) is proposed and investigated by TCAD simulations. This structure features the P+ pillar structure at the side of collector and exits a gap of N-buffers above N+ collector. The P+ pillars increase the distributed resistance below the buffer layer during turn-on transient, show bipolar mode, and eliminate the snapback phenomenon. Accordingly, the structure eliminates the snapback phenomenon with a smaller half-cell pitch of 10~μm, making that the device is more reliable and suitable for parallel connection. For the same forward voltage drop, the turn-off loss of the PPC structure is reduced by 34%. [ABSTRACT FROM AUTHOR]

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure. [ABSTRACT FROM AUTHOR]

This brief first time presents single-event burnout (SEB) simulation results for conventional AlGaN/ GaN gate field plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the first time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high field region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/ $\mu \text{m}$ striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ($\tau $) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected. [ABSTRACT FROM AUTHOR]

This paper introduces the anode-via vertical field plate Schottky barrier diode (AVFP-SBD) structure as an enhanced breakdown voltage AlGaN/GaN SBD, using the 2-D ATLAS Silvaco software. The breakdown voltage enhancement is achieved by integration of the lateral field plate (LFP) and vertical field plate (VFP) into the AlGaN/GaN SBD. The simulation results indicate that the VFP not only provide a uniform electric field along the channel, but also distributes the internal electric field on the side of the anode evenly. We show that the proposed structure significantly enhances the breakdown voltage of the conventional AlGaN/GaN diodes, i.e., from −246 to −354 V. Moreover, optimal breakdown voltage of −2301 V is achieved using the SBD with anode-via both LFP and VFP, through an integration of the LFP into the AVFP-SBD. Such breakdown voltage enhancement is achieved without any deterioration in the forward characteristics of the diode. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of the single-event burnout (SEB) in the floating field ring (FFR) termination of a power MOSFET for the first time. We investigate the SEB triggering mechanism and SEB performance based on a 140-V typical FFR termination, and find that the structure is sensitive to SEB because of a sharp temperature rise appearing at the p+ base/n-drift junction. A 140-V hardened FFR termination (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also studied in this paper that can demonstrate much better SEB performance without sacrificing the basic characteristics compared to the standard one. In addition, the hardening mechanism is explained, and the performances of the hardened structures with different buffer layer thickness are discussed. As a result, the safe operating area can reach the value of the breakdown voltage when the thickness achieves or exceeds 3~\mu \textm . [ABSTRACT FROM AUTHOR]

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( R \mathrm{\scriptscriptstyle ON,\mathsf {sp}} ) decreases from 142.9 to 48.2 \textm\Omega \cdot \mathsf cm^\mathsf 2 , and the gate–drain charge ( Q {\mathsf {gd}} ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

This paper presents an optimized split-gate-enhanced trench MOSFET with dual channels (DSGE-UMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance ( R {\mathrm{\scriptscriptstyle ON}\text {-sp}} ) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot. [ABSTRACT FROM AUTHOR]

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop. [ABSTRACT FROM PUBLISHER]

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power trench accumulation mode field effect transistor (ACCUFET) for the first time. In this device, a p+ base region is used to deplete the n− base region to achieve a low leakage current density, and the blocking voltage is supported by the n− drift region. We find that the depth of the p+ base region determines both the leakage current density and SEB performance, as a result, there is a tradeoff relationship between the two characteristics. The 60 V hardened power ACCUFET shown in this paper could demonstrate much better SEB performance without sacrificing the current handling capability compared with the standard UMOSFET. The hardened structure mentioned in this paper indicates that an n buffer layer is added between the epitaxial layer and substrate layer based on a basic power device. As a result, the safe operating area (SOA) of the 60 V, 80 V and 100 V hardened ACCUFET discussed in this paper could reach the value of breakdown voltage when the buffer layer is over a certain value, that can realize safety operation throughout entire LET range. [ABSTRACT FROM PUBLISHER]

In this letter, a high-current kink effect free Z-gate polycrystalline silicon (poly-Si) thin-film transistor (ZG-TFT) is proposed and demonstrated. The ZG-TFT, which is formed by a raised source/drain (RSD) region and a split channel (SC) structure, reveals better device performance. Our experimental results show that the ON-current of ZG-TFT is about two times higher than that of a conventional single top gate TFT, and the leakage current is greatly reduced simultaneously. In addition, the high drain electric field is considerably reduced by the RSD structure, and the SC design can further effectively suppress the kink effect. Therefore, a better ON/OFF current ratio and a higher drain breakdown voltage can be achieved. [ABSTRACT FROM PUBLISHER]

A camel diode (CD) gamma-ray dosimeter with dual semifloating gates (SFGs) is presented. The SFG diode performs the function of collecting holes accumulated in the potential hump of CD, and hence controls the barrier height. With the silicon depletion instead of oxide as sensitive area, the sensitivity of the dosimeter is enhanced, while the volume is reduced compared with the conventional dosimeters. Moreover, the dosimeter requires only 2 V bias to reset within 1 ms. The numerical simulation has been carried out with Sentaurus TCAD. As a result, a linear dependence of threshold voltage on absorbed dose of the gamma rays was obtained with a sensitivity of 143 mV/Gy. Due to its high sensitivity, low power, and convenient resetting operation, the design is highly suitable for radiotherapy applications. [ABSTRACT FROM AUTHOR]

This paper introduces an advanced silicon on insulator (SOI) monolithic active pixel structure that leaves small empty volumes (interspace structure) under the SOI electronics wafer to mitigate the back-gate effect and implements silicon sidewall around the complementary metal oxide semiconductor (CMOS) electronics. The interspaces are produced by etching gaps in the oxide grown on top of the sensor wafer (buried oxide, BOX) and aligned with the CMOS channels in the electronics wafer above. The silicon sidewall surrounding the CMOS electronics is connected to the conductor layer. Two-dimensional and three-dimensional physical level simulations are presented to compare this novel structure with the nested well structure and double SOI structure. The results demonstrate that the proposed design could eliminate radiation total ionizing dose effects and reduce the parasitic capacitance between the electronics and sensor. Besides, the impact of varying the applied bias voltage and the p-well dimension on charge collection efficiency has also been studied. [ABSTRACT FROM AUTHOR]

In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm ^2 /Vs, and the specific ON-resistance and the BV were 1.64 \textm\Omega \cdot cm^2 ( V\mathrm {GS}= 15 V, V\mathrm {DS}= 1 V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation. [ABSTRACT FROM AUTHOR]

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power planar vertical double-diffused MOSFET (VDMOSFET) with localized carrier lifetime control. A low carrier lifetime control region (LCLCR) is introduced to accelerate the recombination rate of the generated holes caused by an ion’s impact. The optimal localized range with LCLCR in epitaxial layer has been investigated. The SEB inhibition mechanism with LCLCR is analyzed and discussed. A VDMOSFET with localized LCLCR can operate like a normal VDMOSFET and can have improved SEB performance effectively. In addition, the leakage current density in breakdown characteristics of VDMOSFET is studied based on the variation of carrier lifetime. [ABSTRACT FROM PUBLISHER]

This paper presents 2-D numerical simulation results of single-event burnout (SEB) for hardened power U-shaped gate MOSFET (UMOSFET) with Schottky diode (SD-UMOSFET). In this device, a Schottky diode is integrated into every unit cell of power UMOSFETs. We find that the Schottky contact can leak off the generated holes caused by an ion's impact, and the SEB threshold voltage can be improved. The hardened structure means the addition of an N buffer layer based on a power UMOSFET here. So, the 70 V hardened power SD-UMOSFET discussed in this paper contains a Schottky diode and an N buffer layer, which can work normally without affecting steady-state characteristics. The reverse recovery characteristic and SEB performance of hardened SD-UMOSFET are both enhanced effectively. The reverse recovery time decreases 49%, the reverse recovery current peak decreases 56%, and the softness factor increases more than 100% when the hardened SD-UMOSFET is compared with the standard UMOSFET. In addition, the SEB threshold voltage increases to 64 V, which is 91% of the rated breakdown voltage. [ABSTRACT FROM PUBLISHER]

In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the p^+ plug region structure is proposed. The p-pillar could modulate the electric field of the drift region with the split-gate in 3-D and simultaneously brings electric field peaks at the sidewall junction between p-pillar and n-drift region. Thus the split-gate enhanced with p-pillar (SGEP) UMOS could increase the drift region doping concentration, reduce the on-state-specific resistance, and maintains the breakdown voltage as compared with the super junction and split-gate RSO UMOSs. Numerical simulation results show that the charge imbalance endurance of SGEP is also largely increased. [ABSTRACT FROM PUBLISHER]

In this letter, an improved 4H–SiC step trench-gate power metal–oxide–semiconductor field-effect transistor (MOSFET) with a p-n junction in the trench is proposed. The step trench significantly reduces the ON-resistance of the device. And the p-n junction in the trench reduces the gate charge. Compared with the conventional p+ shielding trench MOSFET structure, simulation results show that the specific ON-resistance and gate charge of the proposed device are improved by 26.4% and 34.7%, respectively. A 43.4% improvement in the figure of merit (including the breakdown voltage and ON-resistance) is also observed. [ABSTRACT FROM PUBLISHER]

In this letter, we propose a novel trench power MOSFET structure with a p-n junction in trench to reduce the gate charge. We utilize the 2-D device simulator, ATLAS, to investigate the characteristics of the proposed structure and compare with the conventional structure. As a result, the proposed structure exhibits 49.5% enhancement in gate-charge Q\mathrm {\mathbf {g}} as compared with the conventional structure, without degrading the other electrical characteristics. [ABSTRACT FROM PUBLISHER]