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This paper proposes a new recognition algorithm for shockable arrhythmias for patients suffering from sudden cardiac arrest. In this paper, by using gabor wavelet transform (GWT), useful and effective spectrum features for electrocardiogram (ECG) are extracted. The proposed recognition algorithm based on spectrum features can achieve good performance comparing with the existing results, i.e. the result of this paper is useful.

We make an effect evaluation method of bum treatment based on image processing for quantitative evaluation of the treatment progress. We first converted the color space of image from RGB color space to L∗a∗b∗ color space and divided image using SLIC Super pixel algorithm. Subsequently, we separate a transplanted skin and burned skin using support vector machine (SVM). As a result, in our proposed method, the average of each of the evaluation indexes recorded a value of 85% or more.

Serious arrhythmic events in most of patients suffering from sudden cardiac arrest are Ventricular Fibrillation (VF) and Ventricular Tachycardia (VT). For these serious arrhythmic events, the timely employment of an electrical defibrillator may lead to successful results. From this viewpoint, widespread deployment of Automated External Defibrillators (AEDs) has been suggested and the most important component in AEDs is accurate and quick detection of these events by means of an appropriate algorithm. However quick and accurate detection of ventricular arrhythmia is not easy. In this paper, we analyze ECG data by using Gabor Wavelet Transform (GWT) and on the basis of the analysis results, we propose a new detection algorithm. Finally, we evaluate the proposed detection algorithm.

Three dimensional transparent conductive oxide-less dye-sensitized solar cells (3D-TCO-less DSCs) consisting of a flexible porous titania sheet are reported. The flexible titania sheet is composed of a dye stained porous titania layer and a mesh sheet acting as the backbone. Flexible TCO-less DSCs, tandem DSCs, TCO-less cylinder DSCs and TCO-less cubic DSCs are fabricated and their fundamental photovoltaic performances are reported.

We proposed a new MOSBD, which integrates MOSFET and Schottky Barrier Diode (SBD) in a single chip. The features of the device are that the SBD are fabricated on fine mesa of less than 0.2μm, surrounded by trenches and optimally distributed inside the high density UMOS. We show that the distributed layout of the SBD inside the MOSFET cells is effective to reduce the reverse recovery charge (Qrr), output charge (Qoss(SBD)) and the forward voltage drop (Vf(SD)) In addition, and the forward voltage drop (Vf(SBD)). In addition, integrated high density UMOS realizes low on-resistance of 18mΩmm2at Vgs=4.5V. The developed MOSBD achieved 46% reduction of chip size, compared to conventional MOSBD and low leakage current even in 175°C high temperature condition. The developed MOSBD successfully increases the conversion efficiency, compared to the discrete solution of MOSFET with external SBD.

This paper reports, for the first time, the development of 500 V, 3 A single chip inverter ICs. The chip size of the IC is 7.1/spl times/5.2 mm/sup 2/, which is only 30% larger than that of 500 A, 1 A inverter ICs. The chip size reduction has been realized by 35% improvement in lateral IGBT on-resistance and an optimized layout of LIGBT unit cells and bonding pads.

This paper experimentally verifies that high-voltage lateral IGBTs fabricated on SOI of less than 5 /spl mu/m exhibit high switching speed without the need for any special device design. This paper also verifies, for the first time, that thin SOI is a promising candidate for 200/spl deg/C high-temperature operation, because switching speed does not deteriorate at high temperature. >

The breakdown voltage of a conventional SOI device is limited because it requires a thicker buried oxide as well as a thicker silicon layer. A new SOI device structure and its substrate are proposed to break through these constraints. The proposed new SOI is characterized by a SIPOS (Semi-Insulating POly-crystalline Silicon) layer inserted between the silicon layer and the buried oxide. Since the SIPOS layer effectively shields the influence of the substrate bias, 600 V breakdown voltage SOI diodes and lateral IGBTs were successfully realized using a 0.8 /spl mu/m SIPOS layer and 0.8 /spl mu/m buried oxide.

A method of carrier lifetime measurement is proposed for accurate power device simulation. It requires the value of independent electron ( tau /sub n/) and hole ( tau /sub p/) lifetimes. Reverse recovery time and the electron-beam-induced junction current of Si p/sup +/nn/sup +/ diodes were measured to obtain the high injection carrier lifetimes ( tau /sub H/) and tau /sub p/, respectively. tau /sub n/ were deduced by extracting tau /sub p/ from tau /sub H/ on the basis of Shockley-Read-Hall theory. tau /sub n/ of the nonirradiated samples and samples irradiated at electron fluxes of 3*10/sup 13/ cm/sup -2/, 5*10/sup 13/ cm/sup -2/, and 7*10/sup 13/ cm/sup -2/ were 3.1 mu s, 600 ns, 360 ns, and 300 ns, respectively. For the same samples, tau /sub p/ were 2.6 mu s, 72 ns, 51 ns, and 33 ns, respectively. These results indicate that tau /sub n// tau /sub p/ values are about one for nonirradiated samples and seven to nine for electron-irradiated samples. >

We report, for the first time, the development of 5 ampere multi-channel lateral IGBTs on SOI. The new LIGBTs are characterized by a plural number of parallel stripe poly-silicon gates and resultant plural number of channels, which enhances electron injection and attains a large current capability. The developed LIGBTs conduct current density over 120 A/cm/sup 2/ at the drain voltage of 3 V and simultaneously achieve a fall-time below 300 ns. The LIGBTs have excellent current capability and short circuit withstanding capability of DC 300 V with 500 A/cm/sup 2/ of drain current even at 200/spl deg/C.

Trench isolated 60 V BiCDMOS processes on bonded 2 /spl mu/m thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200/spl deg/C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 /spl mu/m rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges.