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Objective: To develop and verify a CMOS bone-guided cochlear implant (BGCI) microsystem with electrodes placed on the bone surface of the cochlea and the outside of round window for treating high-frequency hearing loss. Methods: The BGCI microsystem consists of an external unit and an implanted unit. The external system-on-chip is designed to process acoustic signals through an acquisition circuit and an acoustic DSP processor to generate stimulation patterns and commands that are transmitted to the implanted unit through a 13.56 MHz wireless power and bidirectional data telemetry. In the wireless power telemetry, a voltage doubler/tripler (2X/3X) active rectifier is used to enhance the power conversion efficiency and generate 2 and 3 V output voltages. In the wireless data telemetry, phase-locked loop based binary phase-shift keying and load-shift keying modulators/demodulators are adopted for the downlink and uplink data through high-Q coils, respectively. The implanted chip with four-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 μA. Results: Electrical tests on the fabricated BGCI microsystem have been performed to verify the chip functions. The in vivo animal tests in guinea pigs have shown the evoked third wave of electrically evoked auditory brainstem response waveforms. It is verified that auditory nerves can be successfully stimulated and acoustic hearing can be partially preserved. Conclusion and Significance: Different from traditional cochlear implants, the proposed BGCI microsystem is less invasive, preserves partially acoustic hearing, and provides an effective alternative for treating high-frequency hearing loss. [ABSTRACT FROM AUTHOR]

A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 $\mu \textrm {V}_{\mathrm {rms}}$ and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5–3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies 25 mm2. Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression. [ABSTRACT FROM AUTHOR]

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pull-up switch to withstand 4 times the nominal supply voltage (4 × V DD). With the dc input voltage of 3.3 V, the regulated three-stage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pull-down current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm2 for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test. [ABSTRACT FROM PUBLISHER]

A 3 MHz-to-1.8 GHz, 94 \mu\ W-to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses the same type of delay lines for cyclic delay determination and coarse locking is proposed and used to achieve the design goals of small footprint and fast locking for a large operating frequency range. In addition, a new delay structure is developed for the cyclic delay units and coarse delay line. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, the automatic bypassing of the cyclic operation is developed and used to reduce power consumption during high-frequency operation. Through the use of proposed techniques, the active area is reduced to only 0.0153 mm^2, and the operating frequency range is from 3 MHz to 1.8 GHz. The measurement results show that the proposed ADDLL achieves a peak-to-peak jitter of 3 ps with 9.5 mW power consumption when operated at 1.8 GHz. [ABSTRACT FROM PUBLISHER]

A configurable-bandwidth charge-domain filter (CDF) with bandwidth calibration and clock-pulse modulation (CPM) is proposed. The bandwidth calibration scheme controls the insertion loss at a pre-specified frequency by modulating the feedback gain and delay; this helps the CDF to suppress the sinc distortion and thus achieve near-ideal brick-wall filtering. For multi-frequency compensation, a multi-stage CDF architecture is utilized to organize the feedback delay. Together with non-decimation filtering, the noise folding effect as well as the chip area can be reduced. On the other hand, to provide a stable gain under variable channel bandwidth, a CPM scheme is proposed; it adjusts the clock period with a fixed pulse width by zero-insertion. Implemented in a 65-nm CMOS technology, the proposed CDF achieves 58.9-dB adjacent-channel rejection (ACR), 85.5-dB stop-band attenuation (SBA), 41-dB conversion gain, and 19.5-MHz channel bandwidth at 320-MS/s input-sampling rate. Furthermore, for input-sampling rates range from 300 to 480 MS/s, the channel bandwidth can be configured from 5 to 26 MHz. At 1.2-V supply, the chip consumes 8.4-mW power and occupies 0.52-mm² area. [ABSTRACT FROM AUTHOR]

In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A\astVDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-VTH, (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both ‘High’ and ‘Low’ sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A\astVDDmin is ~50% lower than that of conventional 8T SRAM devices. [ABSTRACT FROM AUTHOR]

A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the front-end sub-ADC to synchronize with that of the sample-and-hold (S/H) in the multiplying digital-to-analog converter (MDAC). The prototype ADC, implemented in a 90-nm CMOS process, digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled (with the default sub-ADC sample point set at the midpoint of the delay range). The prototype with calibration circuits fully integrated on chip consumes 12.2 mW and occupies 0.26-mm^2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm^2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise and distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band. [ABSTRACT FROM AUTHOR]

A fully integrated direct-conversion tuner is implemented in 0.13 μm CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing 11P3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm2 die area. [ABSTRACT FROM AUTHOR]

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pull-up switch to withstand 4 times the nominal supply voltage (4 × V DD ). With the dc input voltage of 3.3 V, the regulated three-stage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pull-down current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm 2 for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.