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A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7–13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.

A 28 nm CMOS Software-Defined Transceiver (SDTRX) enabling High-Speed Data (HSD) streaming, including Ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at the lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a DAC-based TX and a smart PLL system. It operates over a 0.4-to-1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple TX-RX loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia SoCs and is, to the authors' knowledge, the first reported transceiver front end to enable true high-speed data streaming within home cable networks.

Parylene C has been extensively used as a biocompatible encapsulation material of implantable microdevices. Towards a new understanding of the material's potential, we demonstrate a versatile method that enables the deployment of the material both as an encapsulant and as a H002B; sensing membrane in a single flexible platform using discrete MOSFETs to evaluate its chemical sensing performance. A 40-electrode array was implemented through standard microfabrication techniques on a free-standing 5 μm Parylene film. A thin film (1 μm) of Parylene was finally deposited on top of the array to passivate the electrode tracks. O2 plasma treatment was employed to selectively functionalize Parylene's H002B; sensing capacity. Measured results indicate a chemical sensitivity of 22.8 mV/pH, while the device exhibits relatively low leakage currents (1.2-13.9 nA) and chemical drifts (10-32 mV/h) over a wide pH range (4-10), rendering Parylene a promising material in the field of flexible bio-sensors.

This paper develops a concept of service regime that governs patterns of innovation in services. Based on a synthesis approach, a service regime composed of four dimensions and ten elements is proposed. A dataset of 311 service firms in Taiwan was collected through a postal questionnaire survey. Principal component analysis and cluster analysis reveal a new innovation taxonomy of four service clusters: innovation laggards, process-organizational centric innovators, product-business model centric innovators, and customer involvement centric innovators. We conclude that these four service innovation clusters are service regime-specific, but less sector-specific. The service regime provides deeper insights for managing service firms and theoretical implications for managing innovation in services.

This paper presents current distortion improvement for power compensation with a single-phase bi-directional inverter in a dc-distribution system. For achieving high power quality, the bi-directional inverter can shift the phase of inductor current to compensate reactive power when injecting power into utility grid. In the phase-shift region, the inverter needs to change the switching operation which might result in current distortion, especially near the zero crossing of the line voltage. In this paper, we propose two switching operations, including unipolar and bipolar, to shift the inductor current and improve its current distortion. Experimental results measured from a 5 kW bi-directional inverter have verified the proposed inverter operations.

This paper presents dc-bus voltage control for a three-phase bi-directional inverter in dc-microgrid applications. The bi-directional inverter can fulfill both grid connection and rectification modes with power factor correction. The proposed control includes two approaches, one line-cycle regulation approach (OLCRA) and one-sixth line-cycle regulation approach (OSLCRA), which take into account dc-bus capacitance and regulate dc-bus voltage to track a linear relationship between dc-bus voltage and inverter inductor current. With the OLCRA, the inverter can tune the dc-bus voltage to the desired voltage accurately every line cycle, which can reduce the frequency of operation mode change and current distortion. The OSLCRA adjusts current command every one-sixth line cycle to adapt to abrupt dc-bus voltage variation. The two approaches together can prevent dc-bus voltage from dramatic change and improve the availability of the dc-microgrid without increasing dc-bus capacitance. Determination of dc-bus capacitance is also presented in this paper. Experimental results measured from a 10 kVA three-phase bidirectional inverter have verified the feasibility of the discussed control approaches.

This paper presents a single-phase bi-directional inverter with dc-bus voltage regulation and power compensation in dc-microgrid applications. In dc-microgrid applications, a power distribution system requires a bi-directional inverter to control the power flow between dc bus and ac grid, and to regulate the dc bus to a certain range of voltages, in which dc load may change abruptly. This will result in high dc-bus voltage variation. In this paper, we take into account this variation and propose an on-line regulation mechanism according to the inductor current levels to balance power flow and enhance the dynamic performance. Additionally, for power compensation and islanding protection, the bi-directional inverter can shift its current commands according to the specified power factor at ac grid side. Simulated and Experimental results obtained from a 5 kW single-phase bi-directional inverter have verified the analysis and discussion.

A cloud computing environment consists of a huge number of processors and memories, high-speed networks, and various application services to provide a lot of service over the Internet for users. However, there are two critical problems in the Internet service provideri¦s (ISP): unfair and unbalanced problems produced by dispatching tasks without considering the character and the workload of servers. Therefore, an efficient Dynamic Cloud Cluster Election Mechanism (DCCEM) is proposed to achieve load balance of resource deployment in this paper. The proposed approach is based on the combination of Combined Input-Cross point Buffers (CICB) and Cloud Virtualization Management (CVM) to distinguish and store the different patterns of service requirements, and then send them to appropriate cloud clusters according to the loading states of specific services, as capacity of CPU, memory, and storage. The simulation results show that DCCEM can dispatch tasks fairly and achieve load balancing for each cloud cluster.

In summary, the idea of a transparent electrets loudspeaker is proved in the present research, and the prototype of it will be available soon.

This paper presents design and development of a dc-distributed system with grid connection for residential applications. The system configuration is first described, including green power generator, energy storage element, dc appliance & equipment, and monitor & control center. For realizing the system, the kernel modules of bi-directional inverter, bi-directional charger/discharger, MPPT and dc appliance have been developed, and they are also introduced in this paper. A virtual house has been built in the CCU campus to demonstrate the system operation, from which test data and the critical issues being worth further study are presented.

Ultra-high-vacuum (UHV) deposited Ga 2 O 3 (Gd 2 O 3 ) [GGO] has been employed for passivating InGaAs and Ge, without using any interfacial paissivation layers (IPLs). The GGO/InGaAs and /Ge metal-oxide-semiconductor capacitors (MOSCAPs) have exhibited low capacitance-equivalent-thickness (CET) of less than 1nm in GGO, low interfacial densities of states (D it 's) ∼ 1011eV−1cm−2, and thermal stability at high temperatures. The high-quality GGO and interfaces of GGO/InGaAs, and /Ge enable the fabrications of inversion-channel InGaAs and Ge MOS field-effect-transistors (MOSFETs) using a self-aligned process, leading to high drain currents, transconductances (G m ), and carrier mobilities.

This paper presents an experimental switched-reluctance generator (SRG) based distributed power system with common DC grid and single-phase AC 220/110V 60Hz outputs. First, a SRG with suitably designed power converter and control scheme is constructed to generate robust DC 48V output. Then it is boosted to establish a 400V common DC grid by a current-fed push-pull (CFPP) DC/DC converter. Well-regulated output with galvanic isolation is obtained by the developed converter. Finally, a typical load-side single-phase three-wire (1P3W) transformerless 220V/110V inverter is developed. A master and a slave robust control schemes are proposed to yield good and balanced sinusoidal output voltage waveforms under varied system load conditions.

Due to the uncertainties of wind speed and various system states, to make the wind plant (WP) operates more efficiently, it is essential to maintain a fine match between the WP generated power and the wind power that can be accommodated into the connected transmission network. In the paper, for a WP with certain number of the wind turbine generator (WTG), each with a specific capacity, the proposed Monte Carlo simulation (MCS) approach is used to obtain the operational efficiency estimated by the average wind power that the power system can actually derive and with this information, how many WTG are suitable for the WP is thus suggested. The results also provide the information which parts of the network should be reinforced such that the operational efficiency of the WP can be improved.

A novel magnetic generation of ultrathin film was discovered by the surface magneto-optical Faraday effect (SMOFE) in ultrahigh vacuum (UHV). The use of SMOFE measuring system is due to the natural color of the ZnO(002) substrate was light yellow and transparent. In this presented article, we are going to show how to accomplish the experiment in the first paragraph and to obtain the magnetic property of the sample. First, a clean (10×10×0.5 mm3) ZnO (002) crystal surface was bombarded by Ar+ plasma. Second, the Co ultrathin film was epitaxially grown on the substrate. The magneto-optical signals of the Co/ZnO film can distinguish the thickness between ultrathin and thick range from the observation of typical hysteresis loops. At a very thin thickness range approximate to atomic layer (∼0.2 nm), we can not observe any magnetic signal. Further, was Interestingly, the ZnO sample with Co coated film then appears magneto-optical intensities by a low-energy nitrogen plasma sputtering for several minutes. We checked the N/Co/ZnO composition near the surface regime by Auger Electron Spectroscopy (AES). It is a strong evidence to explain the result related to the generation of the ferromagnetism.

We have achieved high device performance in self-aligned inversion-channel InGaAs MOSFETs, as well as a CET of it ≤ 1011 eV−1cm−2, and high-temperature thermal stability withstanding >850°C RTA in GGO and a CET of 2 on InGaAs. Remarkable device performances in self-aligned, inversion-channel Ge MOSFET using GGO without any interfacial passivation layers (IPLs), and inversion-channel and accumulation type GaN MOSFET's with high k's as gate dielectrics have also been attained. Interfacial characteristics including energy band parameters were studied using x-ray photoelectron spectroscopy (XPS).

Feverish researches on III–V MOSFETs using high-K/metal gates are carried out for beyond the 22–16 nm node CMOS technology. For integrated circuits, however, precise control of the threshold voltage (Vh) is very critical, which has not been widely studied for III–V MOS devices. Very impressive device performance in terms of drain currents and transconductance has been achieved in inversion-channel In 0.53 G 0.47 As MOSFETs [1, 2]. To work on the lower In-content in InGaAs based inversion-channel devices may alleviate the adverse affects like drain-induced barrier lowering (DIBL) and band-to-band tunneling (BTBT). In this work, we report a systematic study on n- and p-type Al 2 O3/Ga2O3(Gd 2 O3) [GGO]/In0.2Ga 0.8 As/GaAs MOS capacitors (MOSCAPs) using metal gates Al, TiN, and Ni of work functions of 4.1, 4.8, and 5.2 V, respectively. We demonstrated for the first time nearly ideal characteristics of the In 0.2 Ga 0.8 As based MOSCAPs, and remarkably well-controlled V th .

The surface Fermi level unpinning in InGaAs has been realized with high κ dielectric growth using molecular beam eitaxy (MBE) and atomic layer deposition (ALD). Furthermore, world-record device performances in self-aligned inversion-channel InGaAs MOSFET and a capacitance equivalent thickness (CET) of ≤ 1 nm in Ga 2 O 3 (Gd 2 O 3 ) and ALD-HfO 2 on InGaAs have been achieved.

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

This study uses data envelopment analysis and Bayesian networks in e-learning systems evaluation and classification, respectively. By maximizing the weighted summed-outputs-to-weighted-summed-inputs ratio, we obtain the scores of individual as well as groups of reviewers from relative efficiency perspectives. The efficiencies are used as training data to construct the classification model for further decision and pre-evaluation in e-learning systems performance.

In this paper, inversion n-channel GaN MOSFETs using atomic-layer-deposited (ALD) Al2O3 as a high k gate dielectric is demonstrated for the first time electrical performance close to those of the silicon based MOSFET. Device performance are markedly improved compared to the previous results of GaN MOSFETs with high k dielectrics.

We report concepts and modeling results on nonmagnetic semiconductor heterostructure spin devices, including resonant tunneling spin filters, bi-directional resonant tunneling spin pumps, and resonant spin lifetime transistors.

Medial Axis Transform (MAT) is a representation that encodes an object with symmetric (medial) axes in the object interior. MAT has been employed in a variety of applications such as pattern recognition, biological shape analysis and robotic motion planning. This work considers the problem of planning robot paths using a Probabilistic Roadmap (PRM) approach when obstacles create "narrow passages" in the robot collision-free space (the free-space). Past studies suggest that the performance of PRM planners degrades considerably in the presence of narrow passages. However, experiments also show that the dilation of the robot's free-space may dramatically alleviate the narrow-passage problem. Here, a novel MAT-based method is presented to "skinnify" the robot and/or the obstacles, hence to dilate the robot's free-space. A new PRM strategy exploits the dilated free-space to efficiently construct paths through narrow passages. Simulation results validate the use of the proposed MAT-based skinnification technique.

Multimedia traffic sources with tight latency constraint, arising in sessions such as data query, image and video transmissions, can be very bursty and are inefficient to be serviced with a dedicated high-speed link. On wireline networks, bursty traffic is statistically multiplexed to fully utilize the link capacity. In light of recent proposals for wideband CDMA (WCDMA) to service multimedia data, there is a similar need to develop wireless network architectures with flexible bandwidth allocation to facilitate statistical multiplexing. To address this issue, we compared the throughput performance of two promising WCDMA configurations, high speed CDMA (HS-CDMA) and multi-code CDMA (MC-CDMA). HS-CDMA assigns each user a single code with small spreading gain to enable a high transmission rate when it is needed. In contrast, MC-CDMA employs codes with a large spreading gain but permits a user to acquire more than one code. As expected, the throughput of a configuration depends on the receiver structure as well as the operation scenarios like power and SNR constraints. When matched filter receivers are applied, HS-CDMA fares better in most occasions. When multi-user receivers are used, both configurations deliver the same throughput except the situation when the total power is bounded.

The dielectric breakdown of the ferroelectric ceramics PZT 55/44 and PZT-8 were studied at room temperature. Two kinds of breakdown phenomena were observed. In one the sample cracks into several pieces after breakdown, and in the other one or more gaseous channels through the sample appear. The dielectric loss and conductivity of the samples as well as the relationship between the amplitude and duration of field imposed on the sample were measured. The dependence of these parameters on the breakdown mechanism was also studied. >

In this article we present a VLSI implementation of the wavelet based High-Speed Pyramid (HSP) transform algorithm which can be used for lossy hierarchical image coding. The HSP chip features include computation of the forward or inverse HSP transform, user selectable level dependent quantization, generation of zerotree flag bits and testability circuitry. The symmetrical chip structure permits the 5 by 5 pixel array size to be enlarged to 9 by 9 by connecting four chips together. In this way a larger block of image pixels can be processed at the same speed. Details of the general chip design, the replicated cell, additional circuitry and performance estimates are discussed.

The shaping of the subreflectors is done to improve the illumination, spillover, and blockage efficiencies, while the shaping of the main reflector is done to obtain uniform phase distribution. There are two different shaped subreflectors in each system, with one being a dichroic which is attached to the other solid subreflector. The dichroic is a trislot array resonant at Q-band to allow Q-band signal to pass through and reflect K-band. The whole subreflector assembly is rotated with respect to the solid subreflector axis to achieve conical scan at K-band for the tracking of the satellite. A computer program which is the extension of the second version of the Numerical Electromagnetic Code Reflector Antenna Code has been used to analyze these shaped dual-reflector antennas. A geometrical theory of diffraction approach is used to calculate the subreflector pattern and the far-out sidelobes of the main reflector. Aperture integration is used to obtain the main beam and near-in sidelobes. >