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One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices

The effects of gate notching profile defects on transistor performance in cell NMOSFETs of low-power SRAM devices with 0.12 /spl mu/m channel length were investigated. Experimentally, it was found that gate notching profile defects cause serious degradation of the transconductance and the transistor drive current. TSUPREM4 simulations showed that the degradation of transistor characteristics is related to the penetration of the gate notching into the channel region over the source/drain (S/D) extension region and the rapid reduction of gate electric field. Moreover, we found that the degradation of transistor performance is more sensitive to notch depth than notch height.

This paper presents the properties for CoSi/sub 2/ junction used to realize embedded DRAM and logic (EDL). In high thermal processes for EDL, TiN capping shows considerably better junction leakage and device characteristics than Ti capping.

A 1.8 V 4 Gb DDR SDRAM for low voltage and high speed at full density has reduced inter-bitline coupling noise in the twisted open bit line architecture. Amplifier sensitivity and sensing margin are improved by gain-controlled pre-sensing and active calibration of the bitline reference voltage. For noise-immune power-stabilized operation, three circuit schemes suitable for the SDRAM are presented: (i) twisted open bitline (TOB) architecture; (ii) gain-controlled pre-sensing (GCP); and (iii) reference bitline calibration (RBC). The TOB scheme eliminates the coupling noise between adjacent BLs by holding neighboring bitlines stable at the reference voltage with the open readout and sensing using a reference BL from the adjacent block. The GCP scheme increases the sensing margin and speed by employing transconductance-matched pre-amplification. The RBC scheme actively mimics the cell data retention characteristics and yields an optimal voltage level for the reference BL from the charge-shared voltage from replica BL pairs. Together with a chip-size-efficient core signal repeating architecture, these schemes ensure reliable low-voltage and high-speed cell and core operation.