64 results on '"Velenis, D."'
Search Results
2. Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G
3. Characterization of Impact of Vertical Stress on FinFETs
4. In-situ Investigation of the Impact of Externally Applied Vertical Stress on III-V Bipolar Transistor
5. High-Speed TSV Integration in an Active Silicon Photonics Interposer Platform
6. Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O
7. Processing active devices on Si interposer and impact on cost
8. Active-lite interposer for 2.5 & 3D integration
9. Active-lite interposer for 2.5 & 3D integration
10. Demonstration of a cost effective Cu electroless TSV metallization scheme
11. Semi-additive Cu-polymer RDL process for interposers applications
12. Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond
13. Wafer thinning and back side processing to enable 3D stacking
14. Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices
15. Electrical characterization method to study barrier integrity in 3D through-silicon vias
16. 3D stacking using ultra thin dies
17. Development of cost-effective biocompatible packaging for microelectronic devices
18. Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers
19. Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance
20. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections
21. Block placement for reduced delay uncertainty in high performance clock distribution networks
22. Effects of parameter variations and crosstalk on H-tree clock distribution networks
23. 3D stacking using ultra thin dies.
24. Cost effectiveness of 3D integration options.
25. An IC-centric biocompatible chip encapsulation fabrication process.
26. On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.
27. Impact of 3D design choices on manufacturing cost.
28. Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.
29. Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.
30. Buffer sizing for delay uncertainty induced by process variations.
31. Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths.
32. Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C–V Technique.
33. Thermal stability of copper Through-Silicon Via barriers during IC processing.
34. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections.
35. Active-lite interposer for 2.5 & 3D integration.
36. Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling
37. Power Supply Variation Effects on Timing Characteristics of Clocked Registers
38. Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths
39. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
40. Buffer sizing for delay uncertainty induced by process variations
41. Effects of crosstalk noise on H-tree clock distribution networks
42. Clock tree layout design for reduced delay uncertainty
43. Design issues and considerations for low-cost 3D TSV IC technology.
44. Clock tree layout design for reduced delay uncertainty.
45. 3D integration: Circuit design, test, and reliability challenges.
46. Effects of crosstalk noise on H-tree clock distribution networks.
47. Power supply variation effects on timing characteristics of clocked registers.
48. Effects of parameter variations and crosstalk noise on H-tree clock distribution networks.
49. Delay modeling using ramp and realistic signal waveforms.
50. Effects of parameter variations on timing characteristics of clocked registers.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.