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Photovoltaic modules from a utility-scale field experienced power loss by light- and elevated temperature-induced degradation (LeTID). Samples of one of the affected monocrystalline silicon cells were cored and extracted from the module packaging and encapsulation. One of the cell fragments was processed using a regeneration cycle of applying short-circuit-rated current in forward bias at 85°C for 2 weeks, while the other fragment was kept in its outdoor-degraded LeTID state. Both samples were scribed to form 2-mm diameter isolated areas using a femtosecond-pulse-width laser micromachining system. Both isolated areas contained front grid line segments which were wire bonded to larger contact pads, and the samples were probed in a cryostat linked to a deep-level transient spectroscopy (DLTS) system. Using DLTS, a majority-carrier, hole-trap defect was detected on each sample with an activation energy of 0.42 eV. The LeTID-degraded sample, however, had a larger signal corresponding to a trap density of 1.1x1013 cm-3, which was about five times larger than the 2.1x1012 cm-3 trap density of the regenerated sample.

Electron traps are detected from vertical n+-GaAs/n−-InGaP/p+-GaAs diodes with deep-level transient spectroscopy (DLTS). Combining lock-in window (t w ) varying DLTS and double-correlation DLTS (DDTLS), we assign the electron traps to surface states at the sidewalls of the diodes. The methodology is introduced in the paper.

The performance of silicon carbide bipolar devices is limited by the material quality of substrates and epitaxial layers. There are many aspects, one of which is the deep level defects in the epitaxial layer, that affect the quality of materials. N-type 4° off-axis Si-face silicon carbide epitaxial layers were investigated by deep level transient spectroscopy (DLTS), which includes C-V/I-V measurement, DLTS signal spectrum measurement and Arrhenius fitting analysis processes. The energy level position, concentration and capture cross-section of the deep level defects were obtained accurately after the measurement and analysis. Z 1/2 defect was found to be a dominant deep level for all the as-grown samples because it existed in all the samples we characterized. So Z 1/2 defect is widely distributed on epitaxial layers. The largest defect concentration in all samples is Z 1/2 defect, which means that it was obviously the most influential defect type in this work. In addition to Z 1/2 defects, three other deep levels had been found which were RD 1/2 , EH 5 and the one with defect energy level position near 1.209eV.

We have studied changes of sub-gap defect states in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) by means of photoinduced transient spectroscopy (PITS). It is found that the sub-gap states in the channel region of a-IGZO TFTs were drastically modified as back-channel etch process proceeded. The change was due to in-and out-diffusion of hydrogen atoms in the channel region of a-IGZO TFTs, which affects the performance of the a-IGZO TFTs.

SiO 2 /SiC interfaces have been under intensive research, because the quality of the interfaces can significantly affect the performance and reliability of SiC power devices. For offering microscopic insights on the generation of interface defects, here we describe the application of our novel scanning probe microscopy method called local deep level transient spectroscopy (local DLTS) to a thermally oxidized Si-face 4H-SiC epitaxial layer. Our sample is an off-axially grown epitaxial layer which is intentionally modified to have wide flat terraces and macro-stepped features instead of typical terraces separated by atomic steps. A spatially resolved map of the interface defect density shows that the macro-steps have a significantly higher interface defect density than the wide flat terraces. The result suggests that high interface defect densities on typical off-axis SiO 2 /4H-SiC stacks might be related to the steps created during the step-controlled epitaxial growth. Local DLTS is useful for the microscopic evaluation of the interface quality.

A modeling method of deep level transient spectroscopy (DLTS) using circuit simulation with a MOS capacitor compact model which takes into account influences of deep level traps is proposed. In the proposed method, DLTS measurement procedures are described by transient analysis of circuit simulation. Stable numerical convergence is obtained even for the case in which carrier traps with wide range of time scales are included. Through case studies, it is proved that this method is a robust and versatile theoretical tool to predict DLTS signals, which helps to understand DLTS results and to optimize DLTS measurement conditions. Furthermore, the method is applied to several capacitance measurement methods discussed in literatures concerning GaN MIS capacitors, which ensures the practical ability of the proposed simulation approach.

High resolution observation of density of interface states (Dit) at SiO 2 /4H-SiC interfaces was performed by local deep level transient spectroscopy based on time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). The sizes of the non-uniform contrasts observed in the map of D it were in the order of several tens of nanometers, which are smaller than the value reported in the previous study (>100 nm). The simulation of the tr-SNDM measurement suggested that the spatial resolution of tr-SNDM is down to the tip radius of the cantilever used for the measurement and can be smaller than the lateral spread of the depletion layer width.

The local deep level transient spectroscopy, which measures traps with high lateral resolution using sharp tip, was investigated as functions of DC bias. The results showed that the physical origin which was detected by local-DLTS was mainly interface trap. Furthermore, two-dimensional (2D) quantitative profiling of interface traps as a function of time constant was demonstrated. Comparison between images of different time constant revealed that interface traps with different time constant had different lateral distribution, which suggests that 2D distribution of interface traps depends on their energy level. These results show that local-DLTsis promising for microscopic investigation of interface traps.

In this study, we investigated defect levels and their densities by deep-level transient spectroscopy (DLTS). In BaSi 2 epitaxial films, there is a hole trap with a density of N T = 1013 cm−3 at 0.27 eV from the valence band edge. This is interpreted to originate from Si vacancies. We also discuss the minimum lifetime of BaSi2 from the viewpoint of the Shockley-Read-Hall recombination model.

Deep level transient spectroscopy (DLTS) is widely spread characterization method of traps in semiconductor material, however, it is hardly applicable to devices with a high leakage current. Due to this reason, DLTS results for narrow-band semiconductor devices are still lacking. In many cases, low-frequency noise spectroscopy (LFNS) can overcome the limitations of DLTS, because current fluctuations instead of the transient capacitance are analyzed. In the paper, the duality and complementarity of deep level transient spectroscopy and low-frequency noise spectroscopy is demonstrated and discussed for InAs/GaSb superlattice mid-wavelength IR detector with unipolar bulk barrier. The trap activation energy E A = 300 meV is obtained with both techniques; however, LFNS detects a few other trap activation energies, namely E A = 240 meV, 180 meV, and 130 meV, while the DLTS found also E A = 490 meV.

Radiation degradation characterization method for solar cells embedded with quantum dot (QD) layers using Photo-Induced Current Transient Spectroscopy (PICTS) is proposed in this study. Contrary to Deep Level Transient Spectroscopy (DLTS), PICTS is capable of comparing directly photo-current degradation to radiation induced defects for p-i-n structure solar cells, which is a basic structure of QD solar cells. GaAs p-i-n solar cells with 50 In 0.4 Gao 0.6 As QD layers are fabricated by Molecular Beam Epitaxy (MBE) and the radiation degradation is investigated by PICTS measurement. The current-voltage characteristics under AM0, 1 sun condition is also investigated and the degradation of solar cell performance is discussed by comparison to defect levels obtained from PICTS spectra. GaAs p-i-n solar cells without QDs are also investigated for comparison.

High resolution 20 μm n-type 4H-SiC epitaxial layer Schottky barrier radiation detectors were fabricated by depositing nickel (Ni) contacts using DC sputtering for both front- and backside. Current-Voltage (I-V) measurements at 300 K showed barrier height and diode ideality factor of ∼1.14 eV and 1.19 respectively. The leakage current at -170V reverse bias was $\sim 1.0 \times 10^{-9}$ A. Capacitance-Voltage (C-v) measurements revealed a doping concentration of $2.9 \times 10^{14} cm^{-3}$. Deep level transient spectroscopy (DLTS) was carried out to investigate defect levels and capture cross sections. Shallow and deep level defects at Ec – (0.14 ± 0.01) eV, Ec – (0.18 ± 0.01) eV, Ec – (0.62 ± 0.02) eV, Ec – (1.42 ± 0.04) eV, and Ec – (1.52 ± 0.03) eV have been found. A 0.1 μCi 241Am radiation source was used to assess the detector performance by pulse height spectroscopy (PHS) and the detector showed energy resolution of 0.38% full-width half maxima (FWHM) for alpha particles at 5447 keV.

Excellent open circuit voltage $(V_{oc})$ reported by Si Heterojunction (Si-HJ) solar cells has been a topic of considerable interest among the PV community. One of the reasons attributed to this large $V_{oc}$ is the reduction of interface recombination due to the presence of an inversion layer at a-Si:H/cSi interface. Here, we employ deep level transient spectroscopy (DLTS) measurements of silicon heterojunction cells (Si-HJ) to probe process induced interface traps at the a-Si:H/cSi interface. Interestingly, contrary to literature reports, we find both majority and minority peaks in differently processed Si-HJ solar cells - a result which could have interesting implications towards performance optimization.

Cu 2 ZnSn(S, Se) 4 (CZTSe) is an earth-abundant semiconductor with potential for economical thin-film photovoltaic devices. Short minority carrier lifetimes contribute to low open circuit voltage and efficiency. Deep level defects that may contribute to lower minority carrier lifetimes in kesterites have been theoretically predicted, however very little experimental characterization of these deep defects exists. In this work we use admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS) to characterize devices built using CZTSSe absorber layers deposited via both coevaporation and solution processing. AS reveals a band of widely-distributed activation energies for traps or energy barriers for transport, especially in the solution deposited case. DLTS reveals signatures of deep majority and minority traps within both types of samples.

Based on 70 keV, 170 keV protons and 5 MeV protons, the interaction between oxide charge and displacement defects in 3DG112 NPN bipolarjunction transistors (BJTs) was investigated. Both ionization and displacement damage can result in the current gain degradation of BJTs. The degradation of the transistor varies linearly with increasing the irradiation fluence for 170 keV and 5MeV protons but nonlinearly for 70 keV protons, implying that the 170 keV and 5 MeV protons mainly induce displacement damage to the NPN BJTs, while the 70 keV protons cause non-bulk damage. Based on the calculation, the end of the range for 5 MeV protons is much deeper than the base and DLTS probed region. 70 keV protons can only arrive at oxide layer, and 170 keV protons exhibits a maximum displacement damage in the base region. The displacement defects in based-collector junction of 3DG112 transistor induced by 5 MeV proton exposures, and the oxide trapped charge caused by 170 keV and 70 keV proton irradiations, were discovered by DLTS technology.

A new technique for microscopically evaluating insulator-semiconductor interface traps is proposed. The proposed technique is applied for SiO 2 /SiC stack structure and 2-dimensional imaging of interface traps is performed.

Schottky barriers were fabricated on 50 µm thick n-type 4H-SiC epitaxial layers. The effective doping concentration was calculated from high frequency (1 MHz) capacitance-voltage (C-V) measurements and was found to be ∼ 9×1014 cm−3. Using a thermionic emission model, an effective barrier height of 1.22 eV and an ideality factor of 1.6 were calculated from the room temperature forward current-voltage (I–V) characteristics. The barrier height was also calculated from the C-V measurements and was found to be slightly higher compared to that obtained from I–V measurements, which suggests a spatial variation of surface barrier height across the device surface area. Capacitance mode deep level transient spectroscopy (DLTS) in the temperature range 80 to 800 K revealed the presence of four electron traps located in the energy range of 0.17 – 1.6 eV below the conduction band edge (Ec). Three deep level defects at Ec-0.67 eV (Z×), Ec-1.04 eV (EH5), and Ec-1.67 eV (EH6/7) are detected along with one shallow level defects at Ec-0.17 eV (Ti(c)). The capture cross-sections and defect densities were studied systematically through DLTS measurements before and after isochronal annealing in the temperature range of 100 – 800 K. Among different defects, Z½ and EH6/7 are found to be very stable in the entire isochronal annealing range. The defects' parameters are evaluated and correlated with previous studies.

High resolution Schottky barrier alpha detectors have been fabricated on 20 µm n-type 4H-SiC epitaxial layers. The junction properties of the detectors were studied by current-voltage (I–V) and capacitance-voltage (C-V) measurements. A thermionic emission model applied to the forward I–V characteristic revealed an effective surface barrier height of 1.72 eV and a diode ideality factor of 1.18 suggesting uniform spatial distribution of surface barrier height. The C-V measurements revealed a doping concentration of 1.8×1014 cm−3 which ensured a fully depleted (∼20 µm) detector at bias voltages as low as ∼70 V. Alpha spectroscopy measurements revealed an energy resolution of 0.5% for 5.48 MeV alpha particles. The performance of these detectors is limited by the presence of microscopic and macroscopic defects. Deep level transient spectroscopy (DLTS) studies revealed the presence of Ti(c), Z½, and possible Ci1 defect centers. An improvement in detector resolution to ∼0.3% was observed after edge termination while evaluating effects of surface defects on device performance.

Deep Level Transient Spectroscopy (DLTS) is a technique to determine the electrical characteristics of an electrically active defect in a semiconductor. A measurement system is developed to detect defects in a semiconductor in a LabView environment. A more accurate method namely Fundamental Frequency Deep Level Transient Spectroscopy (FFDLTS) is proposed as one of the methods to analyze the defect level depth.

Boron ions will be implanted at 150 keV down the axis of n-type silicon. Deep-level transient spectroscopy will be used to study the range, concentration and species of the created defects. A comparison to crystal-TRIM results will be made in order to refine model parameters.