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Electromagnetic (EM) side-channel analysis (SCA) is a prominent tool to break mathematically-secure cryptographic engines, especially on resource-constrained devices. Presently, to perform EM SCA on an embedded device, the entire chip is manually scanned and the MTD (Minimum Traces to Disclosure) analysis is performed at each point on the chip to reveal the secret key of the encryption algorithm. However, an automated end-to-end framework for EM leakage localization, trace acquisition, and attack has been missing. This work proposes SCNIFFER : a low-cost, automated EM Side Channel leakage SNIFFing platform to perform efficient end-to-end Side-Channel attacks. Using a leakage measure such as Test Vector Leakage Assessment (TVLA), or the signal to noise ratio (SNR), we propose a greedy gradient-search heuristic that converges to one of the points of highest EM leakage on the chip (dimension: $N \times N$ ) within $O(N)$ iterations, and then perform Correlational EM Analysis (CEMA) at that point. This reduces the CEMA attack time by $\sim N$ times compared to an exhaustive MTD analysis, and by $> 20\times $ compared to choosing an attack location at random. We demonstrate SCNIFFER using a low-cost custom-built 3-D scanner with an H-field probe ( $50, 000 commercial EM scanners, and a variety of microcontrollers as the devices under attack. The SCNIFFER framework is evaluated for several cryptographic algorithms (AES-128, DES, RSA) running on both an 8-bit Atmega microcontroller and a 32-bit ARM microcontroller to find a point of high leakage and then perform a CEMA at that point.

ROCKY is a recently introduced countermeasure against fault attacks for authenticated encryption algorithms. It is based on the random rotation of the internal state. In this work, we evaluate the effectiveness of ROCKY as a countermeasure against side-channel attacks. We implement four different types of FPGA-oriented architectures of Xoodoo: an unprotected version and three different versions protected with ROCKY. Xoodoo is used as round function of Xoodyak, which is a scheme in the NIST lightweight cryptography standardization competition. For the experimental setup, the SAKURA-G target board with Spartan-6 FPGA is used. The evaluation of the results is done through test vector leakage assessment (TVLA). This is the first work looking into the side-channel security of the ROCKY countermeasure.

The COVID-19 pandemic has forced many people to do work from home (WFH). In practice, networks used in homes generally do not apply security and lack awareness of possible cybersecurity threats. The development and use of security systems on home networks with inexpensive and practical solutions are highly demanded. Therefore, a device that can detect cybersecurity threats is needed to minimize the risks with practical solutions and affordable costs. This conducted research provides a design of a Snort-based Intrusion Detection System (IDS) device that was applied to the Raspberry Pi 3 Model B+. TaZmen Sniffer Protocol (TZSP) is also implemented to analyze network traffic and The SHA3 algorithm used to calculate periodical hash value. This paper implements five types of attacks, there are ICMP BlackNurse, SYN Flood, SMTP Brute Force, RDP Brute Force, and Web Phishing. In addition, this research using the 'htop' program to perform performance testing, and ’sha3sum' program to conduct the test vector algorithm. The system has 100% accuracy rate detecting the attacks and requires less than 50% CPU and 10% RAM. So that the system can be applied to home networks as a practical and affordable cost solution in order to implement cybercrime security.

This work deeply studies the identification of stuck at faults and its corresponding test vectors for a circuit. The circuit under consideration is a 2 – to – 1 multiplexer designed by NAND gate developed with the FinFET technology. The main constraint on design of the circuit is its area and power consumption. The design is simulated and its functionality is verified using Microwind 3.8. The simulation of PODEM algorithm for the designed circuit is proposed in this paper. The netlist generated from this simulation is adapted to simulate the PODEM algorithm to detect the faults. The simulation is carried out in MATLAB2019b and identified the fault location with a input test vector.

11This work is partially supported by the research project sponsored by the Synopsys Inc., USAAdvancements in data science have enabled various fields to achieve unparalleled performance and efficiency enhancement. Different domains of Artificial Intelligence (AI) held the center of interest for researchers, academic and industrial practitioners throughout the last decade. When it comes to the low power testing, it still has a wide range of possibilities where existing methods and techniques can be made more efficient as well as faster with the integration of AI. In this proposal, first, we have come up with a new test vector reordering technique that attempts to reduce both shift and capture power during testing. Secondly, we claim that the use of AI models can significantly speed up such techniques where repeated simulation-based value estimation remains an essential bottleneck. We verify our claim by engaging a deep neural network (DNN) based predictive model to replace the repetitive simulation-based method on this new reordering technique. Experimental results show that the AI-based framework can speed up the simulation-based framework by 162 times, on average.

The generation of high-speed digital vector is one of the main problems in IC testing. With the increasing of the working frequency of digital circuits, the speed and accuracy of digital test vector are also required to be higher and higher. Based on FPGA high-speed transceiver, this paper provides a method of generating high-speed digital integrated circuit test vectors. It also introduces the specific implementation of high-speed digital pattern synthesis and broadening, and explains the possible situations in it. The resulting test vector speed is up to 800Mbps and the edge positioning accuracy can reach 40ps.

Every cryptographic design has to be secure to fulfil its function properly. As side-channel attacks are becoming easier and easier to perform, designers of secure circuits must pay attention to implementing various countermeasures against these attacks. However, in some cases, their hard work can be thwarted if automatic optimizations invalidate the defences. This work explores the effect of synthesis parameters settings on the vulnerability of the cryptographic designs implemented in FPGAs to side-channel attacks. It focuses on the implementation of Advanced Encryption Standard (AES) with multiple countermeasures against attacks and evaluates the effect of parameters settings on security using Test Vector Leakage Assessment based on Welch's t-test.

Oscillation-based built-in self-testing (OBIST) enables self-testing of active circuits without the application of a test vector. It is shown that the output f 0 and P osc of a microwave amplifier under OBIST varies under supply rail variation (which causes variation in P1db and mid-band gain). It is shown that both parameters can be detected by differential power detection, but that the approach lends itself better to P osc -based detection than /o-based detection. Two distinct oscillation modes are identified, which may be exploited for future built-in self-diagnosis and self-healing.

As the circuit implementation predominantly focuses on the higher density and performance with the technology scaling, more adverse types of faults and effects have been investigated by the system designers. Naive and compatible testing approaches are required to apprehend the emerging technological issues, and that will ensure high reliability and quality to the systems’ functional behaviors. The unidentified permanent faults, in particular stuck-at faults, have very adverse impacts on the functional quality of circuits under stressful workloads. This paper focuses on the single stuck-at faults simulation and proposing an Artificial-Intelligence (AI) based algorithm for the prediction of Functional Failure Rate (FFR) of each net (netlist wire) for a given set of input patterns. The statistical prediction also provides an improved way of estimating the Functional Fault Coverage (FFC) and the effectiveness of the input test vector. The introduced algorithm is an accelerated methodology which will significantly reduce the time complexity by 60%, while compared to the traditional exhaustive fault-injection approaches. The case study has been conducted with the gate-level circuit of the 10-Gigabit Ethernet MAC.

With the rapid development of system integration and processing technology, especially the emergence of system chip, integrated circuit has entered a new period of development. As the increasing scale of SOC integration and the limited number of pins, it is necessary to build testability design logic to improve its controllability and observability. However, it will lead to the problem of high test power consumption, which will cause great harm to the circuit under test. In this paper, a new test vector seed generation algorithm is proposed. Based on the traditional LFSR reseeding technology, we introduce the low-power test vector reordering algorithm into the test vector coding technology. Because of the different order of the coded test vector seeds applied to the circuit under test, the number of hops in the circuit under test is reduced, and the goal of low-power test is achieved. In order to verify the effectiveness of the proposed scheme for power reduction, we apply it to ISCAS85 partial reference circuit, and the average power consumption reduction is 25.16%. The experimental results show that the algorithm has a good effect on reducing test power consumption.

Deployment of Post Quantum Cryptography(PQC) primitives ensures forward secrecy for today’s communication against tomorrow’s quantum adversary. However, these primitives have to be realized in conventional hardware, which may be vulnerable to side-channel attacks. Therefore, vulnerability analysis of these primitives is essential before deployment. In this paper, a NIST favoured digital signature primitive- SPHINCS is taken for analysis. ChaCha and BLAKE are ciphers that form the building blocks of SPHINCS. These ciphers are based on Addition, Rotation, and XOR(ARX) operations. The literature review has shown ARX ciphers to be vulnerable against implementation attacks. In this work, an effective countermeasure for the aforementioned building blocks is explored. This is achieved through the following: Parallel Prefix Adders are taken for addition operation in these ciphers instead of the native adder in Electronic Design Automation(EDA) tools. Distinct profiles are created which include the cipher using a particular adder with its best-suited implementation style. An optimized version of Threshold Implementation(TI) is adopted on the profiles as a countermeasure for the attacks on the unprotected implementations. Finally, we evaluate the protected profiles’ resistance using Test Vector Leakage Assessment(TVLA) and Deep learning techniques. Such an analysis that follows a generic framework will be straightforward to automate. We believe this will serve to be useful for standardization of Threshold Schemes.

High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in transition delay fault scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases path delay, and thus might result in timing errors, such testing induces unnecessary yield loss in the deep submicron era. It is known that test manipulation methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventionally, these two techniques have been independently studied for a capture power dissipation problem. However, their effects depend on the application results of each other. In this paper, we propose an X-identification-filling method to co-optimize capture power dissipation using a Partial MaxSAT Solver. The method justifies values assigned to propagate target faults to pseudo primary outputs and reduces the number of transitions on as many internal signal lines as possible. Experimental results show that our proposed method reduced the numbers of capture-unsafe test vectors and unsafe faults compared with conventional methods.

During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit under test (CUT), and structural damage as well. In this paper, a new technique has been proposed that can efficiently reorder the test vectors targeting low switching activity in the scan chain. The technique has been verified with ISCAS’89 benchmark circuits. The achieved reduction in switching activity goes up to 12% when compared to the pattern order generated by an automatic test pattern generator (ATPG) tools like ATALANTA.

In order to improve the test efficiency and the test coverage of software in the flight test, we propose an automatic test technology for embedded software in aviation test equipment. It is based on the traditional black box technology, and combines with semi-physical simulation and virtual device modeling technology. This system uses the TA support platform and cooperates with the test case automatic generation component, it can generate test vector sets, provide incentives for devices, and obtain response information synchronously. It enables users to generate test vectors and obtain test results automatically through simple operations. It can effectually reduce the manual repeat workload, improve the automatization of system testing, and enhance the system testing efficiency and quality.

The relevance of the topic is to provide the solution to the problems of creating equipment for test systems of complex electronic products. The goal is to ensure the efficiency test vectors generation devices during the testing of large and extra large integrated circuits. The task is to optimize the generation algorithm according to the criteria of test sequence maximum length and minimum hardware costs. The task of constructing a flowchart for the algorithm of generating the test vectors for creating periodic and irregular test actions is solved (with the test systems operating in a wide frequency range). The result is a structure that combines the generator of test vectors with multiplexing into one channel, which allows implementing a test sequence of up to 1 GHz. Conclusions indicate that the proposed configuration is a compromise between the minimum memory size with long test sequences and fast reloading of the channel without interruption in generation.

High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases path delay, and thus might result in timing errors, such testing induces unnecessary yield loss in the deep sub-micron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low capture power oriented X-filling methods assign logic values to unspecified bits in test cubes to reduce the number of transitions on FFs. However, our goal is to reduce the number of transitions on internal signal lines. In this paper, we propose a low capture power oriented X-filling method iteratively using a Partial MaxSAT Solver which reduces the number of transitions on as many internal signal lines as possible. Experimental results show that our proposed method reduced the numbers of capture-unsafe test vectors and unsafe faults compared with conventional methods.

The SM3-MAC algorithm is a Message Authentication Code (MAC) algorithm based on the SM3 hash algorithm proposed by Office of Security Commercial Code Administration in 2010. In this paper, a masking scheme for SM3-MAC algorithm using key mask is proposed. Then, 5,000 power traces are collected by software simulation with Hamming distance model. We can prove that the unmasked SM3-MAC hardware is vulnerable to first-order power analysis, while the masked SM3-MAC hardware does not have register leakage under the Hamming distance model. After that, the SAKURA-G FPGA board is used to collect two sets of power traces of the masked SM3-MAC hardware, each of which contains 3,000 traces. The Test Vector Leakage Assessment (TVLA) methodology proves that there is a 99.999% chance that no first-order power leakage is detected in the masked SM3-MAC hardware. Finally, the feasibility of second-order power analysis is discussed, and the effects of different pre-processing functions on correlation are investigated. A second-order test has been carried out to analyze the second-order security of the masked SM3-MAC hardware, which proves that there exists second-order leakage.

Side-channel analysis pose a serious threat to many modern cryptosystems. Using Correlation power analysis, attacker may be able to recover the cipher key and therefore jeopardize the whole cryptosystem, which is why many countermeasures are being developed. These countermeasures are typically effective against first-order attacks. However, protected implementations may still be vulnerable to higher-order analysis. In this paper, we compare different approaches to the higher-order analysis regarding their mathematical and performance properties. We focus on Correlation power analysis attack and the test vector leakage assesment using Welch's t-test, we optimize and accelerate discussed algorithms using CPU and GPU, and we present our experimental results and remarks.

Synchronous design has evolved a predominant design methodology owing to its integrity in VLSI digital systems and is highly reliable over efficiency in clock signal. Random pattern test (RPT) generator in synchronous with Simple Genetic Algorithm (SGA) generates test vectors for circuit under test. A novel technique is introduced to reduce test application time; integrating random pattern test generator with SGA is initiated. The generated test vector is compacted through genetic algorithm methods viz., selection, mutation and crossover operators to produce smaller test size. Thus, test time gradually reduces which leads to faster rate of convergence resulting in high fault coverage. Test vectors and test application time minimization, results in achieving efficiency in a design. The defects in the circuit can either be stuck-at-fault or stuck-open fault and stuck-at-fault is widely preferred in circuits. The key feature in novel approach is parallel fault simulation that provides additional performance, which is an advantage for fault propagation to primary output without backtracking. In this paper, we have presented implementation of fault simulation that is carried out on ISCAS'89 sequential benchmark circuits using HOPE simulator. Experimental results show that the proposed parallel fault simulation method outperforms well in contrast to other primitive fault simulators in terms of fault coverage and computational time. Based on implementation results, fault simulator HOPE, incorporating genetic operators' results about 1.4 times faster for ISCAS'89 benchmark circuits.

Test power dissipation is way higher than normal mode power dissipation due to extensive switching activity, which affects the reliability of the device. Switching activity can be reduced by reordering of test vectors without modification in the circuit under test. In this work, a genetic algorithm with simulated annealing is proposed for reordering of test patterns and thereby finding optimum orders of test vectors to reduce overall switching activity at the time of application of test vectors. Hamming distance among consecutive test patterns is minimized in this work for reordering the sequence. Experimental results demonstrate a significant improvement of 16.5% in the reduction of switching activity on ISCAS’89 benchmark circuits.

Locality based prediction has shown excellent performance in difficult multi-step forecasting problems. However, either neighbor search or sparse coding is usually used to define locality, which requires considerable computations. In this paper, we are investigating a locality-based time series forecasting based on bagging trees defined neighborhood. The proposed method is based on finding all the training examples that share the same leaves in the bagging trees ensemble with the test vector. Then we calculate the predicted target value based on the training examples respective weights (how many times each training example share the same terminal node in each tree with the test example). Two types of bagging trees are investigated; (classification and regression). We test our proposed method on the monthly time series data from M3 competition dataset with horizons range (1 to 18). We compare our results with other machine learning and statistical forecasting techniques. The proposed model outperformed almost all other techniques especially in higher horizons.

Physical unclonable function (PUF) has been widely investigated as a potential security primitive. The unexpected and unclonable PUF information usually serves as a unique ID or secret key in various application scenarios. How to retrieve the PUF information securely at a reasonably low cost is then a concern. In this paper, we propose a new scheme to extract the PUF information by scan chain. PUF information is used to monitor the test control port (tc) of some specific scan cells at certain time. The output response under a designer-specific test vector is hence obfuscated. The difference between the obfuscated output and the normal output can be used to deduce the PUF information. By reusing the existing scan chain design, the design for PUF extraction cannot be removed easily and it incurs negligibly low overhead. As the specific test vector and related design detail are both unknown to others except designer, the probability for an attacker to figure out the PUF information is sufficiently low. This scheme to extract PUF information can be applied in metering technique or other security-sensitive scenarios.

The contents in website and social networks are rapidly generated. The opinions and reviews can be analyzed and classified into two classes, positive or negative opinions, by machine learning methods. However, the main issue is how to representing each text as a proper set of variables, a p-feature vector, so that the successful classifiers can be obtained by one of the supervised learning approaches with its suitable parameter setting. In this study, a two-feature vector representing positive and negative moods in each text was prepared by using lists of positive and negative words, and then combined with term frequency - inverse document frequency (TF-IDF) features. kNN and SVM classifiers were comparatively built by this set and also other baseline set to predict each test vector and measure their effectiveness. Data of text Reviews from Yelp, Amazon and IMDB, were experimented with 10-fold cross validation in parameter variation and feature set reduction using PCA. The best Accuracy results across these three datasets, ~0.81-0.87, were yielded by SVM classifiers with each size of the reduced feature sets that is very smaller than the original size.

In recent years, the number of test vectors has increased due to VLSI circuit density and complexity. A test compaction technique can reduce the number of test vectors without losing fault coverage. However, the number of transitioned signal lines per one test vector increases since each compacted test vector detects more faults. Therefore, excessive capture power consumption at scan testing causes the excessive IR drop and it might induce unnecessary yield loss. In this paper, we propose a static test compaction method which guarantees that generated test vectors are capture-safe.

An efficient method is proposed for detecting hard-to-detect stuck-at faults of combinational circuits and generating all tests or one test vector for them. The method is based on the previously proposed efficient methods of constructing the ODNF and ROBDD representations of the observability and stuck-at fault detection Boolean functions, corresponding to a line of the combinational circuit.

Modern circuits with high performance and low power requirements impose strict constraints on manufacturing test generation, particularly on timing test. Delay test is used for performance grading of the circuit. During the application of the test, power consumption has to be less than the functional threshold value, in order to avoid yield loss. This work proposes a new direction to generate power safe test without any changes in DFT (design for testability) structure or existing CAD (computer-aided design) tools. We propose a virtual wrapper circuitry around the circuit under test (CUT), for test generation purpose, which acts as a shield to obtain power safe vectors. The wrapper prohibits the generation of test vector if power consumption exceeds the threshold limits. We consider analytical power models for power analysis of candidate test vector patterns. Experiments performed on benchmark circuits show power safe test generation without coverage loss.

Scan-based side-channel attacks have been gaining a prominence among the malicious attackers. The unprotected scan chains are extremely vulnerable and could be exploited to extract the secret information from a security chip such as an Advanced Encryption Standard (AES) cryptochip. To protect the secret information from being hacked it is utmost necessary to redesign the scan chain with security features. In this paper, we propose a secure scan architecture aiming at the protection of AES cryptochips against scan-based attacks. The proposed idea is based on the principle of test pattern encryption. The major contribution of our architecture is area efficiency and its security features without hampering test, diagnose, and debug capability of the original scan chain. The experimental results and security analysis shows the efficacy of proposed design.

With the constant improvement of side-channel attack technology, people pay more attention to the security of chips and many new assessment technology arise at the historic moment. Currently, one of the most prevailing evaluation technology is TVLA (Test Vector Leakage Assessment), which does not depend on the specific implementation of cryptographic algorithms and the underlying architecture of cryptographic devices, but just utilizes t test to evaluate the possibility of leakage in cryptographic algorithms. Existing TVLA methods carry out t tests on power traces at every sampling point, and evaluate whether or not the algorithms exist leakages in each cryptographic operation, which firstly requires the traces must be aligned strictly. But when the power traces are badly aligned or can't be aligned, the TVLA assessment results are meaningless. In order to resolve this issue, we propose a new leakage assessment methodology. First, we carry out frequency spectrum analysis on the power traces collected in time domain; then, evaluate whether exists a leakage by conducting t tests; finally, we verify the validity and effectiveness of this frequency-based TVLA method.

SRAM-based FPGA covers nearly 60% of the applications, also susceptible to Single Event Upsets (SEUs) due to radiation. Therefore, FPGA-based systems need to be tested and verified. The testing and dependability analysis techniques are most widely used, with fault injection techniques. These approaches are developed in RASP-Fault Injection Tool. These approaches require the deliberate introduction of faults in the target system. In test approach, it is mandatory to obtain minimum test vectors which detect maximum faults. There are many fault models used for that purpose, e.g. bit-flip, stuck-at (1 & 0). In the proposed test approach, the condition of set point value (SP-value) is defined for each fault model. Therefore, the only patterns which can detect faults more than SP-value are collected and called them qualified test vectors. Furthermore, these qualified vectors are used to obtain the compact test vectors for the Automatic Test Equipment (ATE). In our previously proposed test method, we have used the concept of the SP-value method to obtain qualified test vector for FPGA-based designs. We have chosen SP-values in the range of 20% to 50% of the total injected faults in the design. However, in this paper, validation of this selection criterion for the SP-value is presented.

Research in reversible computing has gained importance because of its potential use in low-power design, and also quantum computing. Several works on reversible circuit testing have also been reported. Many fault models have been proposed, some of which have been borrowed from traditional logic. In this paper, we consider the problem of reversible circuit testing, specifically targeting test generation for stuck-at and bridging fault models. It has been shown that [log 2 N] number of test vectors are necessary and sufficient for detection of all inputs bridging faults of a reversible circuit with N inputs. Addition of only one more test vector to an existing test set of single input bridging faults can also detect all single input stuck-at faults. Finally, we provide our experimental results to verify our claim, and also show that the test size is smaller as compared to existing methods.

The cryptographic chip is widely used in government, military, finance, business and other fields, so the requirement of security is very high. The globalization of the integrated circuit supply chains has promoted the rapid development of the industry, but the chip is also vulnerable to malicious modified by the attacker, namely hardware Trojan implanted. The paper proposed a hardware Trojan efficient triggering method in AES cryptographic circuit. The method generated the test vector set by using the proposed optimal expand algorithm, which was used for detecting the AES cryptographic circuit to judge whether AES circuit exist hardware Trojans. Experiment results indicate that the method proposed in this paper can effectively trigger the hardware Trojan, increase the number of hardware Trojans triggered, and improve the trigger efficiency of the hardware Trojan. Thus, it is an efficient triggering method for detecting combinational hardware Trojans in AES Cryptographic circuit.

In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in circuit-damaging high temperature and timing errors, which may cause significant capture-induced yield loss. A low capture power test generation method based on fault simulation using capture safe test vectors in an initial test set was proposed to resolve a high capture power problem. In this paper, we propose a dynamic test compaction method on the low capture power test generation to reduce the number of capture-safe test vectors. In the dynamic test compaction, faults to satisfy the following conditions are selected as secondary faults. The conditions are that fault excitation cubes of secondary faults are compatible with that of a primary fault and secondary faults are located in fanout-free regions which are sensitized by a test vector for a primary fault. Experimental results show that this method reduces the number of capture-safe test vectors by 18% on average.

The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) attacks even after 500,000 encryption traces.

A linear feedback shift register is commonly used as a test pattern generator in LBIST architectures. The test patterns are generated by TPG and are applied to the CUT. The patterns generated by TPG contribute to higher power dissipation in test mode as they lead to higher high switching activity within the CUT. In order to overcome this problem different TPGs are proposed by modifying the conventional LFSR. This paper presents comparative analysis of the seven different low power test pattern generators which are proposed in literature to achieve low power dissipation. An 8x8 multiplexer circuit is used as CUT. Of all the seven TPG’s compared modified clock scheme is the best suited TPG for the low test vector power aware architecture.

A modified Hadamard matrix is proposed and the compression ratio is improved by using the compatible preconditioning method on the basis of transforming and decomposing compression method. With the modified matrix to transform the energy more focused, to better match test sets, and the hardware implementation is relatively simple. With the idea of test vector compaction, input bit-streams of the circuit under test are converted to compatible before the test set is decompose, so that a number of continuously compatible bit-streams are compacted into a single bit-stream. Experiments on the Mintest test set of the ISCAS89 circuit show that both of these methods can improve the compression ratio and the hardware cost is small. The average compression rate of the VIHC coding method can reach 79.69%.

Rolling element bearings are among the most frequently encountered components in the majority of rotating machines. Thus, prognostic and health management (PHM) of rolling bearing plays an important role on the working status of the machine system. Remaining useful life (RUL) prediction is the core of PHM. It's well known that original auto-regression (AR) model is suitable for the prediction of linear and stationary time series. However, the collected bearing vibration signals are non-linear and non-stationary. Moreover, most of the existing techniques require considerable training and parameter tuning which are difficult for practical applications. To overcome these issues, a RUL prediction method for rolling bearing degradation analysis is proposed in this work based on sparse coding (SC) and sparse linear AR model without training and parameter tuning. SC is formulated as a basis pursuit L1-norm problem, where a sparse set of weight is estimated for each test vector. Sparse local linear and neighbor embedding are employed to construct the weight constraint sparse coding (WCSC). Fault trend of rolling bearing is indicated via time-domain features, such as root-mean-square (RMS), peak-to-peak (P2P) and kurtosis. Experimental results well demonstrate the effectiveness of the proposed method for RUL prediction in bearing.

Mass Spectrometry (Surface Enhanced Laser Desorption Time of Flight (SELDI-TOF) assay technique) for proteomics is based on the consistency and reproducibility of protein/peptide expressions. In this study, we opine that mining collections of mass spectra data instead of detailed study of individual ions generated in the course of Mass Spectrometer assay process, will generate discriminative factors for the diagnosis of Alzheimer's Disease (and other diseases in general). This model; Weighted Manhattan Distance Classifier (WMDC), classifies a test vector to the stage label of the most significant train vector to it using Manhattan Distance function and thereafter, classifies a test data point (a collection of test vectors) to the disease stage having the majority of most significant train vectors in it. The disease severity is categorized as normal/control, mild and acute impaired stages, each of which contained 20 SELDI-TOF analysis results. In all, the database contained 60 assay results of saliva analytes or protein source samples under 3 proteinChips; CM10, IMAC30 and Q10. Each laboratory experiment was performed with either low (1800 nJ) or high (4000 nJ) laser energy bombardment level. 90% classification result was obtained with a probability of 0.075 for committing type II error (that is, a test power of 0.925).

Constraint-based watermarking has been proven as an effective means for hardware intellectual property (IP) protection. Scan chain further facilitates field authentication of the watermarks embedded in densely integrated IP cores and serves as an added layer of tamper-evident protection if it is also watermarked. In this paper, we propose a new scan-chain based watermarking scheme that can be used standalone as a reasonably robust copyright protection of hard IP core. During the process of scan chain ordering for test power optimization, the watermark bits constrain the cost of one connection style over the other for certain pairings of scan cells in the minimization process depending on the output of the IP core under the chosen test vector for watermark verification. Thus, the watermark is better obfuscated since both connection styles are possible to be selected at the watermarked locations. Typical attack scenarios are discussed and our experimental results show that strong authorship can be achieved with low overhead on test power incurred.

The problem of determining the sensitization probability of a path by a test vector is investigated. It is important when testing for delay defects due to process variations. An algorithm is presented which has high accuracy. Gate delays are modeled as probability mass functions, and novel operations are introduced that take into consideration circuit reconvergences and path correlations. Experimental results and comparisons with Monte Carlo are presented on the ISCAS'85, ISCAS'89 and ITC'99 benchmarks.

Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.

Online social message classification is an important task for E-Commerce companies to mine and classify the customer opinions. In this paper, we have proposed a first of its kind of an efficient message classification algorithm which is independent of tweet content and considers the set of followers who will retweet during the retweet peaks. By including the followers who will retweet during retweet peaks will get a better sampling of the followers set and reduces the computation and storage complexities drastically. Also, we have eliminated the heavy weight operations like DTW to perform the comparison task between the test vector and training vector. The preliminary experiment results authorize that the proposed system attains an accuracy of 95.96% in classification of tweet messages.

In recent years, the design and synthesis of the reversible quantum circuits have received immense importance in computing world. As the advancement is going on, simultaneously newer challenges are evolving like fault detection and testing in the reversible circuits. To address these issues, proper testing techniques will have to be developed for efficient detection of the faults. In this work, we propose a fault detection scheme for efficient detection of the faults in any type of reversible circuits which may consist of completely positive or completely negative or mixed controlled Toffoli gates. This is suitable for very large circuits with minimum number test vectors. We have tested our scheme on several reversible benchmark circuits. This scheme detects fault as well as localizes the faulty zone. Experimental results are presented and a comparative analysis with recent works has been made.

With the growth of IC technology, power minimization has become a serious concern for the test engineers. Power consumption in test mode is comparatively higher than in functional mode. This high power consumption during testing may generate too much heat which in turn can spoil the circuit under test. Considering the spectrum of low power testing approaches, reduction in dynamic power is viewed here as a sub-problem and resolved through test vector reordering. In this paper, an Enhanced Ant Colony Optimization (EACO) heuristic is applied to sort out an optimal order of test vectors so that switching activity during testing gets lessened. The simulation on ISCAS 85 bench mark test data set has shown promising power reduction when compared with simple ant colony optimization (ACO) and other relevant heuristic approaches.

A huge voluminous of test data creates a major problem in the testing of system-on-a-chip (SOC) design. The advent of compressing test data is mainly due to an inadequate channel capacity and the restricted memory of Automatic Test Equipment (ATE) to store the test data. To overcome these problems, an efficient approach is presented here, namely Cyclic shift based pattern run length (PRL) coding for reducing the volume of test vectors. This new type of Pattern Run Length coding works by compressing the consecutive patterns based on the possible occurrences of four different cases when partitioning the test vector into number of fixed patterns. The experimental results for ISCAS'89 benchmarks show that this proposed technique results in greater compression ratio than former techniques. In addition to, the analytical results show that the cyclic shift based PRL is more suitable when the segment length k increases.

A design optimization method based on dependency model is proposed for Built-in test design in Prognostics and Health Management. Firstly, simplify the dependency model, eliminate the redundant test and merge the fuzzy fault model. Secondly identify the minimum test vector matrix to each fault mode. Under the principles of reliability and costs, determine the optimal test vector, which is used as the criterion of fault detection and isolation. Finally transfer the optimal test vector to embedded diagnosis program and download to the Built-in test. Example shows that the method can diagnose the faults with the lowest test costs and the least tests, and improve the level of fault diagnosis design.

Side-channel attacks are a potent threat to the security of devices implementing cryptographic algorithms. Designing lightweight countermeasures against side-channel analysis that can run on resource constrained devices is a major challenge. One such lightweight countermeasure is shuffling, in which the designer randomly permutes the order of execution of potentially vulnerable operations. State of the art shuffling countermeasures advocate shuffling a set of independent operations in a single round of a cryptographic algorithm, but are often found to be insufficient as standalone countermeasures. In this paper, we propose a two-round version of the shuffling countermeasure, and test its security when applied to a serialized implementation of AES-128 using Test Vector Leakage Assessment (TVLA). Our results show that the required number of traces to break AES-128 implemented using our proposed countermeasure is significantly larger than the implementations using simple one-round shuffling. Furthermore, the new shuffling method has significantly lower overhead of around 1.3 times, as compared to other side-channel countermeasures such as masking that have an overhead of approximately two times.

This paper presents a keystroke dynamics system for mobile devices that employs a statistical distance-to-median anomaly detector. The selected feature set combines the keystroke timing features of hold and latency and the touch screen features of pressure and finger area. The proposed system consists of two modules: training and testing. The aim of the system is to be a research tool to serve two purposes: (i) the generation of a model-independent dataset of keystroke data on mobile devices, for comparison of keystroke dynamics anomaly detectors, (ii) to be used in the evaluation of the authentication performance of the implemented distance-to-median anomaly detector. The system works in the Android environment on Nexus smartphones and tablets. The experimental work has generated a dataset of 2856 records from 56 subjects, 51 records per subject, where each record represents 71 feature elements resulting from the typing of a standard 10-character password. Statistical analysis of the collected dataset showed an equal-error-rate (EER) of 0.049 when using a different pass-mark per subject, and 0.054 when using a global pass-mark for all subjects. The EER results are much lower than previously published results using three distance-based verification models. Also, the false-acceptance-rate at 5% false-rejection-rate is 5.6%, which is much lower than previously published results, but it is still high and needs to be reduced. Evaluation of the testing (authentication) part of the system was carried out through test runs where a genuine user enters his user-id and password as a login attempt, and the resulting test vector of feature elements are matched against the stored template of the user. The login attempt is classified as genuine or impostor based on a preset pass-mark. Conclusions and suggestions for future work are presented.

Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified scan flip-flop design which uses a low cost dynamic slave latch to shift the test vectors and allows the static slave latch to retain the responses from the previous test vector. Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power. Furthermore the proposed scan flip flop design does not use any gating element in functional path, and hence the functional performance overhead is comparatively very less than the previously proposed output gating techniques so far.

In this paper we first present a new test vector multi-bit correction technique for capture power reduction (average and peak) in scan based launch-on-capture transition delay testing of IP cores. Then we present a method which combines the test vector multi-bit correction technique and the dictionary based test data compression method of [11] in order to derive compressed test data with low capture power. Main characteristic of this technique is that the reduction of the capture power is obtained without (or with marginal) degradation of the compression efficiency. The efficiency of the proposed method is verified with simulations.