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Validation of selecting SP-values for fault models under proposed RASP-FIT tool

Authors :
Abdul Rafay Khatri
Ali Hayek
Josef Borcsok
Source :
INTELLECT
Publication Year :
2017
Publisher :
IEEE, 2017.

Abstract

SRAM-based FPGA covers nearly 60% of the applications, also susceptible to Single Event Upsets (SEUs) due to radiation. Therefore, FPGA-based systems need to be tested and verified. The testing and dependability analysis techniques are most widely used, with fault injection techniques. These approaches are developed in RASP-Fault Injection Tool. These approaches require the deliberate introduction of faults in the target system. In test approach, it is mandatory to obtain minimum test vectors which detect maximum faults. There are many fault models used for that purpose, e.g. bit-flip, stuck-at (1 & 0). In the proposed test approach, the condition of set point value (SP-value) is defined for each fault model. Therefore, the only patterns which can detect faults more than SP-value are collected and called them qualified test vectors. Furthermore, these qualified vectors are used to obtain the compact test vectors for the Automatic Test Equipment (ATE). In our previously proposed test method, we have used the concept of the SP-value method to obtain qualified test vector for FPGA-based designs. We have chosen SP-values in the range of 20% to 50% of the total injected faults in the design. However, in this paper, validation of this selection criterion for the SP-value is presented.

Details

Database :
OpenAIRE
Journal :
2017 First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT)
Accession number :
edsair.doi...........6e1372425a85bc0c33aec12bbc8f9864