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The idea of microgrid, smart grid, and virtual power plant (VPP) is being developed to resolve the challenges of climate change in the 21st century, to ensure the use of renewable energy in the electrical grid. For the increasing demand for electricity, raising public consciousness about reducing carbon emission, the microgrid is established which is transformed into a virtual power plant (VPP) or a smart grid with the blessing of modern communication systems, intelligence technology, and smart devices. So, to keep these systems up-to-date and to ensure security, it is important to know the details about the uses and benefits of these systems in the developed world and also to improve control methods and automation, it is important to achieve the present essence of such systems. This paper is focused to contribute to this flourishing area of energy sustainability covering microgrid, smart grid, and virtual power plant by compiling and recapping their recent advancements, technical requirements, control problems, and solutions. The paper is mainly intended to address the role of control strategies applied to the microgrid, smart grid, and virtual power plant towards future energy generation, distribution, management, and security.

A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within TigerMIPS processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting simultaneously a speedup of 70 percent and an energy reduction of 30 percent with coarse-grained ML classification as compared with the baseline TigerMIPS. A speedup of 89 percent is demonstrated with finer granularities with a simultaneous 15.5 percent reduction in energy consumption. [ABSTRACT FROM AUTHOR]

Estimating nutrient content in plants is a crucial task in the application of precision farming. This work will be more challenging if it is conducted nondestructively based on plant images captured in the field due to the variation of lighting conditions. This paper proposes a computational intelligence image processing to analyze nitrogen status in wheat plants. We developed an ensemble of deep learning multilayer perceptron-using committee machines for color normalization and image segmentation. This paper also focuses on building a genetic-algorithm-based global optimization to fine tune the color normalization and nitrogen estimation results. We discovered that the proposed method can successfully normalize plant images by reducing color variabilities compared to other color normalization techniques. Furthermore, this algorithm is able to enhance the nitrogen estimation results compared to other non-global optimization methods as well as the most renowned SPAD meter based nitrogen measurement. [ABSTRACT FROM AUTHOR]

This paper describes the design and the architecture of symbiote coprocessor unit (SCU)—a programmable streaming coprocessor for a heterogeneous reconfigurable logic-assisted data stream management systems (DSMSs) such as symbiote. The SCU is intended for streaming applications with real-time event and data processing that have stricter deadlines, high-bandwidth, and high-accuracy requirements. To meet these requirements, the SCU exploits unique characteristics of DSMSs, such as single-pass tuple processing, windowed operators, and inherent data level parallelism, using a single-instruction multiple-data very large instruction word (SIMD-VLIW) microarchitecture and a novel inverted distributed register file. In order to better explain the instruction set, design, and functionality of the various units in the SCU, this paper also provides a brief overview of SymQL—a procedural query language that we developed to describe the queries that can be executed on the SCU. Finally, this paper presents the performance of SCU using four queries that represent common data stream processing use-cases, one of them being similar to a query found in the Linear Road Benchmark. Using these queries on SCU simulation, we show that the SCU outperforms a software-only DSMS running on an AMD Opteron 2350 quad-core processor by 1.5–42 times. [ABSTRACT FROM PUBLISHER]

The increase in the average age of the world's population over the coming decades will impact several aspects of our lives. In particular, it will increase the demand and challenges of delivering care and assistance to elderly or fragile people. This article describes an ambient assisted living system, called Bridge (behaviour drift compensation for autonomous and independent living), that's based on a set of home services that include a wireless sensor-actuator network for detection of inhabitants' behaviors and a rich, flexible communication system between the inhabitants and a social environment aimed at reassuring both inhabitants and their families. All Bridge solutions have been derived from real needs with the help of a social mediator and tested by users in their living environments. [ABSTRACT FROM PUBLISHER]

In this paper, we consider a wireless cloud computing system in which the service provider operates a data center and provides cloud services to its subscribers at dynamic prices. We propose a joint optimization of scheduling and pricing decisions for delay-tolerant batch services to maximize the service provider’s long-term profit. Unlike the existing research on jointly scheduling and pricing that focuses on static or asymptotic analysis, we focus on a dynamic setting and develop a provably-efficient Dynamic Scheduling and Pricing (Dyn-SP) algorithm which, without the necessity of predicting the future information, can be applied to an arbitrarily random environment that may follow an arbitrary trajectory over time. We prove that, compared to the optimal offline algorithm with future information, Dyn-SP produces a close-to-optimal average profit while bounding the job queue length in the data center. We perform a trace-based simulation study to validate Dyn-SP. In particular, we show both analytically and numerically that a desired tradeoff between the profit and queueing delay can be obtained by appropriately tuning the control parameter. Our results also indicate that, compared to the existing algorithms which neglect demand-side management, cooling system energy consumption, and/or the queue length information, Dyn-SP achieves a higher average profit while incurring (almost) the same average queueing delay. [ABSTRACT FROM AUTHOR]

How to fully apply the characteristics and advantages of light in numerical computation is an important issue that attracts many scholars. Though much research has been done in this field, how to design and realize specific applications or devices is still an issue to be solved. Based on this, we present an architecture and implementation method of modified signed-digit (MSD) optical adder from the point of applicability. In the implementation, we fully consider the different procedures of the MSD addition which including optical logical operation, results decoding, special storage area design, data feedback, control of light path, etc. Meanwhile, we also introduce pipeline mechanism which guarantees that the addition operation is an automatic and continuous process. This is a carry free adder design method which guarantees the addition has high data throughput. It is very suitable to fulfill the large-scale numerical computation. The experiment shows, the MSD adder not only has a reasonable and correct design, but also has high throughput rate, can work efficiently and steadily. [ABSTRACT FROM AUTHOR]

Since introduction of the European qualifications framework (EQF) as one instrument to bridge from learning institutions to competence driven lifelong learning, it remains a challenge for instructors and teachers in higher education to make efficient use of this framework for designing, monitoring, and managing their lessons. This paper presents a software suite for enabling teachers to make better use of EQF in their teaching. The software suite extends course design based on well-defined learning outcomes, monitoring performance and competence acquisition according to the EQF levels, assessment using scoring rubrics of EQF levels and competences in a 360-degree feedback, as well as visualizations of learning analytics and open student models in dashboards for different social perspectives in social planes. This paper includes a case study with 20 teachers who used the software suite in all phases of the course lifecycle for three programming courses. The results show that integrated applications for adopting the EQF in teaching practice are strongly needed. These results also show that the suite can assist teachers in creating contextual awareness, kindling reflection, understanding students and course progress, and inferring patterns of success and failure in competences development. [ABSTRACT FROM PUBLISHER]

Irregular applications, such as data mining or graph-based computations, show unpredictable memory/network access patterns and control structures. Massively multithreaded architectures with large processor counts, like the Cray MTA-1, MTA-2, and XMT, appear to address irregular application requirements better than commodity clusters. However, the research on massively multithreaded systems is currently limited by the lack of adequate architectural simulation infrastructures due to issues such as size of the machines, memory footprint, simulation speed, accuracy, and customization. At the same time, Shared Memory MultiProcessors (SMPs) with multicore processors have become an attractive platform to simulate large-scale systems. This paper introduces a cycle-level simulator of the massively multithreaded Cray XMT supercomputer. The simulator runs unmodified XMT applications. We discuss how we tackled the challenges posed by its development, detailing the techniques implemented to obtain high-simulation speed while maintaining a high accuracy. By mapping XMT processors (ThreadStorm with 128 hardware threads) to host computing cores, the simulation speed remains constant as the number of simulated processors increases, up to the number of available host cores. The simulator supports zero-overhead switching among different accuracy levels at runtime and includes a parametric network and memory model that takes into account contention and hot spotting. On a modern 48-core SMP host, the proposed infrastructure simulates a large set of irregular applications 500 to 2,000 times slower than real time when compared to a 128-processor XMT, with an accuracy error under 10 percent. Emulation is only from 25 to 200 times slower than real time. The paper also presents a case study, where the simulation infrastructure is used to identify bottlenecks in the current XMT architecture and to estimate the performance scaling of a possible multicore design with next generation memory and network interconnect. [ABSTRACT FROM PUBLISHER]

This paper moves a first step towards the creation of Intelligent Domotic Environments (IDE) in real-life home-living. A new Domotic OSGi Gateway (DOG) is presented, able to manage different domotic networks as a single, technology neutral, home automation system. The adoption of a standard framework such as OSGi, and of sophisticated modeling techniques stemming from the Semantic Web research community, allows DOG to go beyond simple automation and to support reasoning-based intelligence inside home environments. By exploiting automatic device generalization, syntactic and semantic command validation, and internetwork scenario definition, DOG provides the building blocks for supporting the evolution of current, isolated, home automation plants into IDEs, where heterogeneous devices and domotic systems are coordinated to behave as a single, intelligent, proactive system. The paper introduces the DOG architecture and the underlying ontology modeling. A case study is also illustrated, where DOG controls a laboratory reconstruction of a simple domotic environment. [ABSTRACT FROM AUTHOR]

We provide an algebraic formalization of connectors in the BIP component framework. A connector relates a set of typed ports. Types are used to describe different modes of synchronization, in particular, rendezvous and broadcast. Connectors on a set of ports P are modeled as terms of the algebra AC(P), generated from P by using a binary fusion operator and a unary typing operator. Typing associates with terms (ports or connectors) synchronization types—trigger or synchron—that determine modes of synchronization. Broadcast interactions are initiated by triggers. Rendezvous is a maximal interaction of a connector that includes only synchrons. The semantics of AC(P) associates with a connector the set of its interactions. It induces on connectors an equivalence relation which is not a congruence as it is not stable for fusion. We provide a number of properties of AC(P) used to symbolically simplify and handle connectors. We provide examples illustrating applications of AC(P), including a general component model encompassing methods for incremental model decomposition and efficient implementation by using symbolic techniques. [ABSTRACT FROM AUTHOR]

Integrated architectures in the automotive and avionic domain promise improved resource utilization and enable a better coordination of application subsystems compared to federated systems. An integrated architecture shares the system's communication resources by using a single physical network for exchanging messages of multiple application subsystems. Similarly, the computational resources (for example, memory and CPU time) of each node computer are available to multiple software components. In order to support a seamless system integration without unintended side effects in such an integrated architecture, it is important to ensure that the software components do not interfere through the use of these shared resources. For this reason, the DECOS integrated architecture encapsulates application subsystems and their constituting software components. At the level of the communication system, virtual networks on top of an underlying time-triggered physical network exhibit predefined temporal properties (that is, bandwidth, latency, and latency jitter). Due to encapsulation, the temporal properties of messages sent by a software component are independent from the behavior of other software components, in particular from those within other application subsystems. This paper presents the mechanisms for the temporal partitioning of communication resources in the dependable embedded components and systems (DECOS) integrated architecture. Furthermore, experimental evidence is provided in order to demonstrate that the messages sent by one software component do not affect the temporal properties of messages exchanged by other software components. Rigid temporal partitioning is achievable while at the same time meeting the performance requirements imposed by present-day automotive applications and those envisioned for the future (for example, X-by-wire). For this purpose, we use an experimental framework with an implementation of virtual networks on top of a time division mu- ltiple access (TDMA)-controlled Ethernet network. [ABSTRACT FROM PUBLISHER]

Although clusters are a popular form of high-performance computing, they remain more difficult to manage than sequential systems-or even symmetric multiprocessors. In this paper, we identify a small set of primitive mechanisms that are sufficiently general to be used as building blocks to solve a variety of resource-management problems. We then present STORM, a resource-management environment that embodies these mechanisms in a scalable, low-overhead, and efficient implementation. The key innovation behind STORM is a modular software architecture that reduces all resource management functionality to a small number of highly scalable mechanisms. These mechanisms simplify the integration of resource management with low-level network features. As a result of this design, STORM can launch large, parallel applications an order of magnitude faster than the best time reported in the literature and can gang-schedule a parallel application as fast as the node OS can schedule a sequential application. This paper describes the mechanisms and algorithms behind STORM and presents a detailed performance model that shows that STORM's performance can scale to thousands of nodes. [ABSTRACT FROM AUTHOR]

On-chip program and data tracing is now an essential part of any system level development platform for System-on-Chip (SoC) Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interlaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each core's debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging Network-on-Chip architectures. [ABSTRACT FROM AUTHOR]

Single chip heterogeneous multiprocessors (SCHMs) are becoming more commonplace, especially in portable devices where reduced energy consumption is a priority. The use of coordinated collections of processors which are simpler or which execute at lower clock frequencies is widely recognized as a means of reducing power while maintaining latency and throughput. A primary limitation of using this approach to reduce power at the system level has been the time to develop and simulate models of many processors at the instruction set simulator level. High-level models, simulators, and design strategies for SCHMs are required to enable designers to think in terms of collections of cooperating, heterogeneous processors in order to reduce power. Toward this end, this paper has two contributions. The first is to extend a unique, preexisting high-level performance simulator, the Modeling Environment for Software and Hardware (MESH), to include power annotations. MESH can be thought of as a thread-level simulator instead of an instruction-level simulator. Thus, the problem is to understand how power might be calibrated and annotated with program fragments instead of at the instruction level. Program fragments are finer-grained than threads and coarser-grained than instructions. Our experimentation found that compilers produce instruction patterns that allow power to be annotated at this level using a single number over all compiler-generated fragments executing on a processor. Since energy is power*time, this makes system runtime (i.e., performance) the dominant factor to be dynamically calculated at this level of simulation. The second contribution arises from the observation that high-level modeling is most beneficial when it opens up new possibilities for organizing designs. Thus, we introduce a design strategy, enabled by the high-level performance power-simulation, which we refer to as spatial voltage scaling. The strategy both reduces overall system power consumption and improves performance in our example. The design space for this design strategy could not be explored without high-level SCHM power-performance simulation. [ABSTRACT FROM AUTHOR]

Enterprise systems interoperability (ESI) is an important topic for business currently. This situation is evidenced, at least in part, by the number and extent of potential candidate protocols for such process interoperation, viz., ebXML, BPML, BPEL, and WSCI. Wide-ranging support for each of these candidate standards already exists. However, despite broad acceptance, a sound theoretical evaluation of these approaches has not yet been provided. We use the Bunge-Wand-Weber (BWW) models, in particular, the representation model, to provide the basis for such a theoretical evaluation. We, and other researchers, have shown the usefulness of the representation model for analyzing, evaluating, and engineering techniques in the areas of traditional and structured systems analysis, object-oriented modeling, and process modeling. In this work, we address the question, what are the potential semantic weaknesses of Using ebXML alone for process interoperation between enterprise systems? We find that users will lack important implementation information because of representational deficiencies; due to ontological redundancy, the complexity of the specification is unnecessarily increased; and, users of the specification will have to bring in extra-model knowledge to understand constructs in the specification due to instances of ontological excess. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort. [ABSTRACT FROM AUTHOR]

Software-defined radio (SDR) clouds combine SDR concepts with cloud computing technology for designing and managing future base stations. They provide a scalable solution for the evolution of wireless communications. The authors focus on the resource management implications and propose a hierarchical approach for dynamically managing the real-time computing constraints of wireless communications systems that run on the SDR cloud. [ABSTRACT FROM PUBLISHER]

The new generation of smartphones has realized the early vision of context awareness. The next step is facilitating real-world impact of more complex recognition, moving toward next-generation opportunistic recognition configurations and large-scale ensembles of networked subsystems interacting with communities of users. [ABSTRACT FROM PUBLISHER]

The class of modern datacenters recently coined as “warehouse scale computers” (WSCs) has traditionally been embraced as homogeneous computing platforms. However, due to frequent machine replacements and upgrades, modern WSCs are in fact composed of diverse commodity microarchitectures and machine configurations. Yet, current WSCs are designed with an assumption of homogeneity, leaving a potentially significant performance opportunity unexplored. In this paper, we investigate the key factors impacting the available heterogeneity in modern WSCs, and the benefit of exploiting this heterogeneity to maximize overall performance. We also introduce a new metric, opportunity factor, which can be used to quantify an application’s sensitivity to the heterogeneity in a given WSC. For applications that are sensitive to heterogeneity, we observe a performance improvement of up to 70% when employing our approach. In a WSC composed of state-of-the-art machines, we can improve the overall performance of the entire datacenter by 16% over the status quo. [ABSTRACT FROM PUBLISHER]