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A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment.

A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment.

Authors :
Ajirlou, Arash Fouman
Partin-Vaisband, Inna
Source :
IEEE Transactions on Computers. Mar2022, Vol. 71 Issue 3, p587-598. 12p.
Publication Year :
2022

Abstract

A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within TigerMIPS processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting simultaneously a speedup of 70 percent and an energy reduction of 30 percent with coarse-grained ML classification as compared with the baseline TigerMIPS. A speedup of 89 percent is demonstrated with finer granularities with a simultaneous 15.5 percent reduction in energy consumption. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189340
Volume :
71
Issue :
3
Database :
Academic Search Index
Journal :
IEEE Transactions on Computers
Publication Type :
Academic Journal
Accession number :
155233169
Full Text :
https://doi.org/10.1109/TC.2021.3057764