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9 results on '"Suthram S"'

1. Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Author

Prasad, C., primary, Jiang, L., additional, Singh, D., additional, Agostinelli, M., additional, Auth, C., additional, Bai, P., additional, Eiles, T., additional, Hicks, J., additional, Jan, C. H., additional, Mistry, K., additional, Natarajan, S., additional, Niu, B., additional, Packan, P., additional, Pantuso, D., additional, Post, I., additional, Ramey, S., additional, Schmitz, A., additional, Sell, B., additional, Suthram, S., additional, Thomas, J., additional, Tsai, C., additional, and Vandervoorn, P., additional

Published
2013
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2. Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

Author

Suthram, S., primary, Sun, Y., additional, Majhi, P., additional, Ok, I., additional, Kim, H., additional, Harris, H. R., additional, Goel, N., additional, Parthasarathy, S., additional, Koehler, A., additional, Acosta, T., additional, Nishida, T., additional, Tseng, H.-H., additional, Tsai, W., additional, Lee, J., additional, Jammy, R., additional, and Thompson, S. E., additional

Published
2008
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3. High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node

Author

Suthram, S., primary, Majhi, P., additional, Sun, G., additional, Kalra, P., additional, Harris, H. R., additional, Choi, K. J., additional, Heh, D., additional, Oh, J., additional, Kelly, D., additional, Choi, R., additional, Cho, B.J., additional, Hussain, M. M., additional, Smith, C., additional, Banerjee, S., additional, Tsai, W., additional, Thompson, S. E., additional, Tseng, H. H., additional, and Jammy, R., additional

Published
2007
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8. Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High (~ 1.5 GPa) Channel Stress.

Author

Suthram, S., Ziegert, J. C., Nishida, T., and Thompson, S. E.

Subjects
SEMICONDUCTOR wafers, TENSILE architecture, BENDING stresses, STRAINS & stresses (Mechanics), SILICON, MICROELECTRONICS
Abstract

A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to ∼700 MPa of process-induced stress. This provides the highest uniaxial channel stress to date at ∼1.5 GPa. The stress altered drain-current is measured for long and short (50–140 nm) devices and the extracted π-coefficients are observed to be approximately constant for stresses up to ∼1.5 GPa. For short devices, this trend is seen only after correcting for the significant degradation in the π-coefficients observed due to parasitic source/drain series resistances ( Rs/d). [ABSTRACT FROM AUTHOR]

Published
2007
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