136 results on '"Sterpone, Luca"'
Search Results
2. EUFRATE: a High-Perfomance Reconfigurable Architecture for Radiation-hardened Telecom Payloads
3. Enhanced Video Surveillance Systems for “Signal for Help” Detection on Edge Devices
4. PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs
5. High-Performance SET Hardening Technique for Vision-Oriented Applications
6. Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs
7. Programmable SEL Test Monitoring System for Radiation Hardness Assurance
8. Radiation Effects in Real-Time Soft Processors: Relating Software Errors to Hardware Faults
9. Programmable SEL Test Monitoring System for Radiation Hardness Assurance
10. Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs
11. PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs
12. High-Performance SET Hardening Technique for Vision-Oriented Applications
13. A Comprehensive Analysis of Transient Errors on Systolic Arrays
14. Analyzing the SEU-induced Error Propagation in Systolic Array on SRAM-based FPGA
15. Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process
16. Proton-induced MBU Effects in Real-time Operating System on Embedded Soft Processor
17. Soft Error Reliability Prediction of SRAM-based FPGA Designs
18. Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices
19. A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC
20. Proton-induced MBU Effects in Real-time Operating System on Embedded Soft Processor
21. Soft Error Reliability Prediction of SRAM-based FPGA Designs
22. SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor
23. SEU Mitigation on SRAM-based FPGAs through Domains-based Isolation Design Flow
24. A New Domains-based Isolation Design Flow for Reconfigurable SoCs
25. FPGA Qualification and Failure Rate Estimation Methodology for LHC Environments Using Benchmarks Test Circuits.
26. An Automated Continuous Integration Multitest Platform for Automotive Systems.
27. A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor
28. Digital Design Techniques for Dependable High Performance Computing
29. On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing
30. Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets
31. In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops
32. Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features
33. A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit
34. Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU
35. An Emulation Platform for Evaluating the Reliability of Deep Neural Networks
36. An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects
37. A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.
38. On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA
39. A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs
40. Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits
41. On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques
42. On the Evaluation of the PIPB Effect within SRAM-based FPGAs
43. Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks
44. A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network
45. Micro Latch-up Analysis on Ultra- Nanometer VLSI Technologies: A new Monte Carlo Approach
46. PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing
47. MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories
48. A Zero-Timing Overhead SET Mitigation Approach for Flash-based FPGAs
49. A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs
50. SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.