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In this paper, readout scheme in ReRAM crossbar array based on sneak current compensation is introduced. This scheme consists of two cycles. In the first measurement cycle, an accurate sneak current is measured which is dependent on the data storage patterns of the crossbar arrays in which the selector ON/OFF ratio is not large enough. In the second cycle, the measured sneak current is subtracted from the total bit line current to predict the cell current accurately. To make the measured sneak current accurate, the crossbar array is divided into many blocks only in one direction so that the impact of array size increase is minimal. The scheme is validated by using HSPICE.

This paper presents methods for optimizing matched filter based GNSS acquisition units. Matched filters become computationally complex when the reference signal length is increased. They have a fixed length in time, which also limits the achievable integration time. In this paper, we show how to design an optimal adder for a large number of single-bit values, and how this can be utilized to build matched filters for multi-bit numbers and multiple inputs. By altering the incoming sample rates, it is possible to adapt the matched filter for changing signal frequency. Employing coherent and non-coherent integration after the matched filter allows enhancing the sensitivity of signal detection with modest implementation size increase.

Fe-Si powder cores have been widely used in energy converting systems and others. In order to use the cores in a several megahertz, silicon content should much higher than that of well-known Fe-6.5% Si alloy. Fe-Si alloys with high silicon content consist of order DO 3 and B2 phases as well as disordered A2 phase. However, the role of DO 3 phase has been controversial in conjunction with good magnetic properties. Cooling rate of water quenched Fe-Si powders during gas-atomization is very high so that the evolution of the ordered phases from non-equilibrium phase changes microstructure and thus magnetic properties of the powder widely during annealing. However, the role of DO 3 phase has been controversial and has not been reported in case of Fe-Si powder up to now. In this study Fe-Si powders with 7 – 11 wt.% Si were gas-atomized into cool water and then sieved to be of a mean diameter of 15 $\mu \mathrm{m}$ . The sieved powders were annealed at $T_{anl}=25-750^{\circ}\mathrm{C}$ for 1 hour in nitrogen atmosphere and then packed into toroid capsules with insulating oil. Structure and magnetic properties were analysed with SEM, VSM, XRD and precision impedance analyser. (200) super lattice peak of B2 phase could be observed in all the as-atomized powders. Detection of (111) peaks of DO 3 phase was possible in the powders annealed at $T_{anl}$ higher than 550, 450 and 25°C in Fe- 7, 9 and 11% Si powders, respectively as shown in Figure. Size of DO 3 phase of Fe-7, 9%Si powder increased with $T_{anl}$ while that of Fe-11 %Si powder was almost unchanged. $H_{c}$ of the Fe-Si powders decreased with increasing $T_{anl}$ . However, there was an increase of $H_{c}$ around evolution temperature of DO 3 phase in Fe - 8, 9% Si powders. Permeability $(\mu^{\prime})$ of the Fe-7, 8, 9% Si powders at 10 MHz decreased with increasing $T_{anl}$ while $\mu$ of Fe-11% Si was almost constant. It was well reported that the electrical resistivity of the Fe-Si alloy changed very much depending on cooling rate in a Si content range of 8 – 20% Si [1]. The reason for the behaviour of $H_{c}$ and $\mu$ with $T_{anl}$ seems to be due to change of electrical resistivity attributed from size increase of DO 3 phase with $T_{anl.}$ More experimental data and detailed discussion will be presented on the conference site.

To achieve the required continuous cost reduction driven by Moore's Law, both miniaturization through technology advances and wafer size increase have been employed in order to maintain the growth and profitability of semiconductor industry. Although some technical analyses have been done for 450 mm migration, little research has been done on economic analysis to justify the decisions and thus suggest appropriate timing for 450 mm migration. This study aims to fill the gap by proposing a preliminary economic analysis to clarify some myths and facilitate further discussions concerning collaborations among the stakeholders including equipment vendors, customers, and chipmakers.

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi- and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been much effort to develop compiler optimizations to improve these paths in order to reduce average-case execution time. In this paper we describe our approach to reduce WCET by adapting and applying optimizations designed for frequent paths to the worst-case paths in an application. Our compiler uses feedback from our timing analyzer to detect the WCET paths through a function that will be subject to aggressive optimizations, reflect subsequent effects on the WCET of the paths due to these optimizations, and to also ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate a number of WC path optimizations and present results showing the decrease in WCET versus the increase in code size.

Summary form only given. In multipulse radiography, electron beam pulses will encounter a background plasma consisting of low atomic weight elements such as water vapor and hydrocarbons, and also vaporized target material, generated by previous pulses. This is important because subsequent pulses penetrating the plasma plumes may suffer spot size increase and misalignment with the radiographic axis if the beam propagation is unstable. The region of this material that is farthest from the target will have a low density and will be collisionless. The beam will collisionlessly penetrate this intervening plasma, rather than pushing a hole through it as would happen in the high density fluid regime. The particle in cell code MERLIN is used to simulate this interaction.

IC manufacturers have stated that the price of 300 mm process equipment should be no more than 1.3 times the 200 mm equivalent equipment. Further, simultaneous technology advances are required for sub 0.25 /spl mu/m processing, creating challenges for the equipment industry. Economic and technical issues differ among process equipment and must be addressed within the context of the process. This paper discusses the aspects of a cost of ownership methodology for wafer size increase and applies the method to high energy ion implantation processes. Depending on the productivity factors related to the number of chips per wafer, significant die cost reductions are available to IC manufacturers over a wide range of 300 mm equipment prices.

The throughput time within a cluster tool can be approximated as T+lt, where T is the fixed throughput time of the cluster, l is the lot size, and t is the average incremental throughput time resulting from a lot size increase of one wafer. Simulations of different cluster tools are used to illustrate and validate the model. The fixed throughput time (T) consists of both an external component associated with loadlock operations such as loading and pumping, and an internal component resulting from dynamic effects such as congestion in the cluster tool. The expressions for the incremental throughput time (t) includes the wafer handling time, and may include the module processing time. This model predicts that the maximum throughput rate of the cluster tool is 1/t, and that this throughput rate can only be achieved if multiple lots can simultaneously access the cluster tool. The model also predicts that this number of lots must increase, for example, as lot size decreases, the number of identical modules on a cluster increases, or lot loading time increases. This model was applied to a CVD cluster tool at Intel Corporation. The model predicted an increase in the cluster's throughput rate of roughly 10% over current operating practice, if one lot could be loaded while a different lot was being processed. The model was verified using a simulator and then on the cluster tool itself.

A 4-Mb DRAM (dynamic random access memory) family which improves upon the performance of the 1 Mb DRAM family is described. While increasing storage density and reducing memory access times, overall chip size is minimally affected. Development of 0.9- mu m CMOS technology for use on the 4-Mb DRAM allowed immediate speed and size improvements over the 1-Mb DRAM. Continual review of lessons learned on previous design insures that each successive DRAM generation is both more efficient in terms of architecture and more reliable in system use. In the case of the 4-Mb DRAM, this dedication to improvement has resulted tin a 20% speed enhancement, moderate size increase (1.6X), and improved reliability results. >

A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of CSPs for a variety of projects. The experience of the Consortium in building more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and the environmental test results has now been published as a CSP guidelines document. The Consortium assembled fifteen different packages with I/Os from 48 to 784 and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring board (PWB). Another test vehicle was designed and assembled by a team member using their internal resources and was identified as TV-H. The TV-H assemblies were subjected to numerous thermal cycling conditions including -55/spl deg/C to 125/spl deg/C with two ramp rates, one thermal cycle with 2/spl deg/ to 5/spl deg/C/min and the other near thermal shock. Cycles-to-failure (CTF) test results to 1,000 cycles and 400 cycles under these conditions are presented for fine pitch ball grid arrays (FPBGAs), CSPs, and wafer level CSPs (WLCSPs). Decrease in CTFs due to ramp rate and die size increase for different I/O FPBGAs with 0.8 mm pitch are compared and analyzed.