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The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (Δ NIT) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (VG) and drain (VD) biases spanning various modes (VG ≤ and > VD) are simulated for low stress VD (< 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained. [ABSTRACT FROM AUTHOR]

Transistor parametric drift due to conduction mode hot carrier degradation (HCD) is reviewed. The time kinetics in n-channel MOSFETs and FinFETs is analyzed for channel length (LCH) variation from ~ 2~μm to ~20 nm and oxide thickness (TOX) scaling from ~20 to ~1 nm, for drain bias (VD) variation from ~8 to ~1 V, and gate bias (VG) chosen to achieve a maximum HCD for a particular type of device. The time kinetics shape variation from long-channel heavily doped abrupt junction devices through moderately long-channel lightly doped drain (LDD) devices to short-channel devices featuring moderately doped source–drain extensions (SDEs) is reviewed. The temperature (T) dependence of HCD and the comparison of dc and ac HCD stress kinetics are reviewed in long LCH at high VD and in short LCH at low VD stress. The observed data are qualitatively explained. [ABSTRACT FROM AUTHOR]

Transistor parametric drift due to conduction-mode hot carrier degradation (HCD) in n-MOSFETs is reviewed, for long- and short-channel length (LCH) devices having different source/drain (S/D) junction structures. The HCD magnitude and time kinetics shape are discussed for stress under different gate (VG) and drain (VD) biases with varying VG/VD ratio, and without and with substrate bias (VB). Post-dc stress kinetics is discussed. The published data are qualitatively analyzed to identify the roles of different underlying physical mechanisms. In part II of this article, impacts of technology scaling and stress temperature (T) and comparison of dc and ac stress are discussed. [ABSTRACT FROM AUTHOR]

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift ($\Delta {V}_{T}$) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain (${V}_{D}$) and gate (${V}_{G}$) voltage space and calculates the generation of interface traps for pure HCD ($\Delta {V}_{\text {IT-HC}}$) and for negative bias temperature instability (NBTI) ($\Delta {V}_{\text {IT-BT}}$), hole trapping ($\Delta {V}_{\text {HT}}$), and electron trapping ($\Delta {V}_{\text {ET}}$) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10- $\mu \text{s}$ delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying ${V}_{G}$ and ${V}_{D}$ stress in the presence of SHE but no HCD. [ABSTRACT FROM AUTHOR]

A compact hot-carrier degradation (HCD) time kinetics model is proposed for conventional, lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured data obtained using different methods such as shift in threshold voltage ($\Delta {V}_{\text {T}}$), linear ($\Delta {I}_{\text {DLIN}}$) and saturation ($\Delta {I}_{\text {DSAT}}$) drain current, and charge pumping current ($\Delta {I}_{\text {CP}}$), for off- and on-state stress conditions. The influences of the gate $({V}_{\text {G}}$) and drain (${V}_{\text {D}}$) bias for large ${V}_{\text {D}}$ range and wide ${V}_{\text {G}}/{V}_{\text {D}}$ combinations, temperature (${T}$), and channel length $({L}_{\text {CH}}$) have been analyzed. The impact of ${L}_{\text {CH}}$ variation on ${V}_{\text {G}}$ dependence of HCD has been modeled. The model parameters are listed for different devices. [ABSTRACT FROM AUTHOR]

Threshold voltage shift ( \Delta \text V\text T ) due to negative-bias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps ( \Delta \text V\text {IT} ), hole trapping in preexisting ( \Delta \text V\text {HT} ), and generation of new ( \Delta \text V\text {OT} ) bulk insulator traps is used to quantify measured data. The model can explain dc stress and recovery data over an extended temperature range (−40 °C to 150 °C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of \Delta \text V\text {IT} , \Delta \text V\text {HT} , and \Delta \text V\text {OT} , and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods. [ABSTRACT FROM PUBLISHER]