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The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field. [ABSTRACT FROM AUTHOR]

Industrial semiconductor electrodeposition plating cells require recirculation of process chemicals with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow translate to a reduction of in-line defects and increased wafer yield. [ABSTRACT FROM AUTHOR]

Doing high throughput high accuracy metrology in small geometries is challenging. One approach is to build easily measurable proxy targets onto dies and make a predictive model based on those signals. We use optical Pattern Shift Response (PSR) proxy targets to build predictive models of the electrical characteristics of devices in the Back End Of Line (BEOL). Given the wide choice of PSR targets, we explore how to select combinations of them to maximise the utility of the features for building an accurate Machine Learning (ML) model; we call this approach Multiplexed Optical Metrology. We also explore the trade-off between chip area dedicated to targets and achievable accuracy. We run ML experiments using different selections of targets measured at different stages of BEOL processing: post-lithography and post-Chemical-Mechanical-Planarisation (CMP). Our results show that a) reasonable predictive performance can be achieved for a reasonable area budget; b) ML model performance across target families varies significantly, thus justifying the need for careful selection of targets; c) longitudinal measurements of targets increases accuracy for no extra area penalty; d) increasing the number of targets gives some improvement in accuracy for a dataset of this size, but relatively small compared to the increase in area budget needed. Ultimately we aim to do die-level yield prediction using these techniques. We discuss how collecting a larger dataset with appropriate yield information is the logical next step to achieving this. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory. [ABSTRACT FROM AUTHOR]

This is a panel paper that discusses the use of Artificial Intelligence (AI) technologies to address production and supply chain level problems in semiconductor manufacturing. We have gathered a group of expert semiconductor researchers and practitioners from around the world who have developed AI solutions for various semiconductor problems. This paper aims to provide their answers to an initial set of questions and provide an overview of the AI developments and empirical studies to make suggestions for future directions in this arena. [ABSTRACT FROM AUTHOR]

Adding an appropriate amount of suitable elements is an effective way to suppress In-Zn-O (IZO) carriers. The influence of different doping concentration Ca incorporation on In-Zn-O oxide-based thin film transistors (Ca-IZO TFTs) was investigated theoretically and experimentally. First-principles calculations show that as the doping concentration of Ca increases, the IZO bandgap gradually widens. Moreover, low-concentration doping of Ca does not significantly reduce carrier density and mobility. A novel high-performance Ca-IZO film has been experimented by a low-cost sol-gel process. And the best Ca-IZO TFT device was achieved when the mole ratio of Ca was 3%. The slight Ca-doped In-Zn-O TFT showed a high on/off current ratio ~106, a high field-effect saturated mobility of 1.4 cm2/Vs, and a positive threshold voltage $(V_{\mathrm{ th}})$ of 7.7 V.

Semiconductor vertical furnaces must achieve even faster and more precise temperature control due to the demand for ever-reducing the minimum feature size or critical dimension in semiconductor chips. Also, the insulation performance of vertical furnaces has improved to reduce power consumption; as a side effect, temperature reduction operation takes longer without active cooling. Therefore, in addition to heaters, vertical furnaces equipped with coolers have emerged to achieve higher productivity, more precise temperature control, and lower power consumption. However, the inability to generate positive and negative control inputs for one of the heaters or coolers poses a challenge for an intuitive controller parameter design. The aim of this paper is to address these issues by proposing an intuitive method for designing a controller in the frequency domain which virtually integrates heaters and coolers. We implemented the controller in a full-scale actual semiconductor vertical furnace and first confirmed that the linearity is high. Furthermore, we experimentally verified that the controller achieves both high-speed, high-precision temperature control and low power consumption. [ABSTRACT FROM AUTHOR]

Given the ubiquity of electronic devices and the urgent need to decrease our footprint in the context of global warming and planetary boundaries, it becomes critical to better quantify the environmental impacts of integrated circuit (IC) production. Our work addresses this question in three successive steps. First, we carry out a review of the data available since 2010 from four different literature categories, i.e., foundry reports, industry roadmaps, scientific literature, and life-cycle assessment databases. Then, we leverage the 27 identified sources to perform both a qualitative and quantitative analysis. We propose 10 features for characterizing the scope of studies while focusing on environmental indicators normalized per cm2, i.e., energy consumption, carbon footprint and water consumption. The analysis results highlight a clear increasing trend of the environmental footprint with CMOS technology downscaling below $0.13~\mu \text{m}$ , despite a significant variation between the sources mainly due to scope mismatch. Finally, we show that environmental impacts per cm2 did not significantly decrease compared to historical values from 1980–2010, whereas the total silicon area produced keeps on increasing by 3.6%/year. Consequently, this work calls for urgently rethinking the road ahead with sobriety to effectively decrease the absolute environmental footprint of the IC production sub-sector. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) is the state-of-the-art converter topology in HVdc transmission applications. The reliability and lifetime of MMCs are strongly dependent on the health of the internal power semiconductors. The operating loss of power semiconductors, which is one of the dominant factors affecting component aging, is not uniformly distributed between the top and bottom switches in the same submodule (SM) due to the dc bias in the arm current. Such loss imbalance leads to differences in lifetime of semiconductors and reduces the reliability of SM. Especially under inverter conditions, the bottom insulated gate bipolar transistor (IGBT) in SM is subjected to a severe thermal stress and has a relatively high failure rate for the thermal vulnerability of IGBT. To extend the lifetime and improve the reliability, this article proposes a component-level loss balancing method. It is achieved by insertion index modification based on a feed-forward gain controller. The proposed method can improve the loss distribution among the top and bottom semiconductors without side effects on ac and dc outputs. Its effectiveness and feasibility are validated through simulation and experimental results. [ABSTRACT FROM AUTHOR]

The Czochralski (CZ) process is the core technology for producing semiconductor silicon monocrystalline (SMC), and it is a complex batch process. However, the crystal growth rate and crystal diameter, which are key quality indicators, are difficult to detect directly online, and the offline calculation process lags seriously, which easily causes blind crystal quality control. Therefore, this paper proposes a data-driven and mechanism-based hybrid model for semiconductor SMC quality variables prediction in the CZ process. Firstly, a data-driven model JITL-SAE-ELM based on just-in-time learning (JITL) fine-tuning strategy is proposed. This model is used to solve the nonlinear and time-varying relationship of the energy transfer process in the CZ process that cannot be accurately described by traditional mechanism models. Here, the SAE-ELM model integrates a stacked autoencoder (SAE) and an extreme learning machine (ELM), which are used to deeply capture the nonlinear and time-varying features of process data. Secondly, according to the hydrodynamics and geometric behavior, a crystal pulling dynamic mechanism model based on the crystal growth mechanism is constructed, which avoids the complicated heat transfer link. Further, considering the unmodeled dynamics caused by model parameter uncertainty during the combination of the energy transfer model and crystal pulling dynamic mechanism model, a crystal diameter compensation model SAE-ELM was developed to improve the prediction accuracy of the CZ process hybrid model. Finally, an industrial data experiment based on a CZ monocrystal furnace illustrates the proposed method. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon field-effect transistors (FETs) in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/ $\mu \text{m}$ (near 20 mA/ $\mu \text{m}$) and an on/off ratio of 106 are achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. Short-pulse measurements are applied to mitigate the self-heating effect induced by the ultra-high drain current flowing in the ultra-thin channel layer. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate that ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration. [ABSTRACT FROM AUTHOR]

Multi-bridge channel field effect transistor (MBCFET) provides several advantages over FinFET technology and is an attractive solution for sub-5 nm technology nodes. MBCFET is a natural choice for devices that use semiconducting layered materials (such as, MoS2) as the channel due to their dangling-bond-free ultra-thin nature and the possibility of layer-by-layer transfer. MoS2-based MBCFET is thus an attractive proposition for drive current boost without compromising on the electrostatics and footprint. Here we demonstrate a 3-level MoS2 MBCFET, where each vertically stacked channel is dual-gated to achieve a saturation current of $174.9~ \boldsymbol \mu \text{A}$ (which translates to $90~ \boldsymbol \mu \text{A}$ per $\boldsymbol \mu \text{m}$ footprint width (@ $2.7~ \boldsymbol \mu \text{m}$ channel length), a near-ideal sub-threshold slope of 63 mV/dec, and an on-off ratio lpzrptGreater108. This work sets the benchmark for layer-material-based MBCFET in terms of the number of parallel channels integrated, simultaneously providing high drive current and excellent electrostatic control. [ABSTRACT FROM AUTHOR]

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of $27.7~\mu \text{A}/ \mu \text{m}$ at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor. [ABSTRACT FROM AUTHOR]

We report on the realization of record low resistance Ohmic contacts to MOVPE-grown heavily Si-doped $\beta $ -Ga2O3 and $\beta $ -(AlxGa1-x)2O3 epitaxial films. Transfer length measurement (TLM) patterns were fabricated on the heavily Si-doped homoepitaxial $\beta $ -Ga2O3 films with electron concentration (n) ranging from 1.77 to $3.23\times 10^{20}$ cm−3. Record low specific contact resistance ($\rho _{c}$) and total contact resistance (${\text{R}_{c}}$) of $1.62\times 10^{-7}\,\,\Omega $.cm2 and $0.023 \Omega $.mm were realized for $\beta $ -Ga2O3: Si films with n $ > 3\times 10^{20}$ cm−3. TLM structures were also fabricated on heavily Si doped coherently strained $\beta $ -(AlxGa1-x)2O3/ $\beta $ -Ga2O3 (x = 12%, 17% and 22%) films. The film with 12% Al composition (n $=1.23\times 10^{20}$ cm−3) showed $\rho _{c}$ of $5.86\times 10^{-6}\,\,\Omega $.cm2, but it increased to $2.19\times 10^{-4}\,\,\Omega $.cm2 for a layer with a 22% Al composition. Annealing the samples post metal deposition has generally led to a decrease in contact resistance, but for high Al content $\beta $ -(AlxGa1-x)2O3, the contact resistance did not change significantly after the annealing process. The low contact resistance values measured in this work are the lowest for ultrawide bandgap semiconductors and are very promising for the fabrication of high frequency power devices. [ABSTRACT FROM AUTHOR]

Based on a double-layered semiconductor nanostructure (DLSN)-InSb/GaSb, we propose a controllable electron-spin filter for spintronics device applications. Electron-spin polarization is induced by Rashba spin-orbit coupling inside the DLSN. Both magnitude and sign of spin polarization ratio can be manipulated by externally-applied electric field or the semiconductor-layer thickness. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Terahertz (THz) electrical signal generation from a photoactive semiconductor device illuminated by an optical pulse is modeled and simulated. Hydrodynamic equations in time domain are numerically solved for both electrons and holes using the discontinuous Galerkin time-domain finite element method (DGTD-FEM) for the high-frequency charge transport that occurs in the semiconductor device. The obtained frequency spectra of photocurrent in various semiconductor materials under illumination of an ultrashort light pulse are presented. The inertia effects and ballistic transport of carriers play an important role to determine the frequency response of these materials, and the developed hydrodynamic model (HDM) solver delivers a transport analysis by predicting higher and wideband frequency capabilities for GaAs and Ge detectors over Si-photodetectors. [ABSTRACT FROM AUTHOR]

Bidirectional photoresponses (BPR) are significant, yet rare in conventional optoelectronic systems. In this letter, we achieve BPR in the inorganic-organic semiconductors hybrid phototransistors (HPTs) by introducing Schottky contact at metal-semiconductor interfaces. The Schottky contact enables the HPTs with distinguishable positive and negative photoresponses to ultraviolet and near-infrared light, respectively, capable of differentiating incident light wavelengths. Our results provide an efficient solution to achieve BPR, promising for wavelength differentiating and advanced optoelectronic sensors. [ABSTRACT FROM AUTHOR]

The nanorod/nanowire arrays of narrow-bandgap semiconductors are a kind of great potential light-harvesting material for photovoltaic devices due to their excellent optoelectrical properties. Here, a $\gamma $ -butyrolactone (GBL) solution-processed inorganic Sb2S3 nanorods on the TiO2 film is developed to fabricate light-harvesting layer for efficient inorganic Sb2S3/TiO2 semiconductor heterojunction thin film solar cells. The morphology, absorption properties, crystallinity and grain orientation of the Sb2S3 nanorods heterojunction film is investigated by scanning electron microscopy (SEM), ultraviolet-visible spectroscopy (UV-vis), X-ray diffraction (XRD) techniques. The inorganic Sb2S3/TiO2 nanorods heterojunction thin film solar cells deliver a champion power conversion efficiency of 4.14%, which is a considerable efficiency for the solar cells based on GBL solution-processed inorganic Sb2S3 nanorods heterojunction thin film. [ABSTRACT FROM AUTHOR]

Conventional field-effect transistors (FETs) based on silicon downscaling are approaching physical limits, and thus, it is urgent to explore additional novel solutions to address this issue. The 2-D semiconductors have unique advantages as the channel material and provide a promising prospect for high-performance FETs in the post-Moore era. In this work, a new 2-D semiconductor, monolayer BeN2, is studied for the FET performance limits through first-principle quantum-transport simulations. Monolayer BeN2 exhibits a graphene-like planar structure with a direct bandgap of 1.3 eV. Transfer characteristics of sub-10-nm BeN2 FETs are thoroughly assessed through scaling gate length. In particular, 2-D BeN2 FETs with 10-nm gate present the ultrahigh ON-state current above $4500\,\, \mu \text{A}/\mu \text{m}$ for high-performance applications. Also, we realize the significant reduction of gate length (only 2.5 nm) against the International Technology Roadmap for Semiconductors (ITRS) requirements through introducing underlap structures. In addition, the performance of single devices based on monolayer BeN2 is evaluated and compared with some of the recently proposed 2-D devices. [ABSTRACT FROM AUTHOR]

The undesirable impacts of solder void defects on the reliability of die packages have prompted stringent requirements on solder void size control in the semiconductor packaging industry. Vacuum reflow process using Pb95Sn5 solder was studied, where critical process parameters within temperature and pressure profiles were varied for enhanced solder void size reduction, in comparison to conventional reflow process. Higher reflow temperature profile, faster pressure pump-down rate, and longer vacuum dwell time above threshold levels are critical conditions required for consistently achieving minimum solder void sizes well below the industry criteria. Application of threshold conditions using large volume reflow oven with industrial settings has achieved the single and the total solder void size over die size well below the standard 2.5% and 5% requirements, respectively, with majority of the samples attained the single and the total solder void size over die size below 1% and 2%, respectively. Solder bond line thickness exhibited a significant influence on the solder void size reduction and thus needs to be administered appropriately during die packaging assembly to achieve the maximum solder void size reduction. [ABSTRACT FROM AUTHOR]

III-V semiconductor lasers are ubiquitous in modern optoelectronic devices, with applications ranging from telecommunication to general lighting. Among the different kinds of laser cavity designs, whispering-gallery mode (WGM) micro-cavity lasers boast outstanding optical performance due to advantages such as ultra-high Q-factor, compact mode volume, and narrow emission linewidth. Over the past decades, research in III-V WGM micro-cavity lasers has progressed rapidly in various aspects, including the fabrication techniques, emission outcoupling methods, and practical applications. In this paper, a comprehensive review is performed on the advances in these aspects. Although III-V WGM lasers are conventionally fabricated with top-down approaches, recent reports have demonstrated the potential of highly-scalable bottom-up methods in fabricating low-loss WGM lasers. Despite the strong optical confinement in III-V WGM cavities, various techniques have been developed to either outcouple WGM emission into waveguides or direct it into free-space with small beam divergence. Finally, recent developments in different applications of III-V WGM micro-cavity lasers are discussed. Other than serving as integrated photonic components, III-V WGM lasers have also displayed exciting potential in other applications such as label-free sensing and the study of cavity quantum electrodynamics (cQED). [ABSTRACT FROM AUTHOR]

This article presents how to design multiband energy selective surface (ESS), which has a nonlinear transmission response to the power of incidence in multiple frequency band. It is demonstrated that ESSs with an arbitrary number of operating bands could be obtained with both parallel and serial LC resonance circuits and each single operating band could be modulated from a passband with low insertion loss (IL) to a stopband with high shielding effectiveness (SE). Furthermore, a dual-band ESS is designed to verify the proposed methods, in which two rectangular resonance rings mounted with Sckotty diodes are used. A 0.5 IL and 30 dB SE are observed at the central frequency of both operating bands with ECM and full-wave simulations. Prototypes are fabricated and measured with a waveguide set-up. There is a good agreement between the simulations and measurements under low-power incidence. However, some differences are observed under high-power incidence. The reason behind is discussed in detail and some measures for improvement are also proposed. The proposed approach provides general guidelines for multiband ESS design and is supposed to obtain wide use in adaptive shielding for high power microwave (HPM). [ABSTRACT FROM AUTHOR]

In capacitive pulsed power supply (CPPS), semiconductors, such as crowbar diodes, can be damaged by surge energy in worst cases, which reduces the reliability of CPPS. The generation mechanism of surge energy is discussed initially. A surgesuppression scheme is presented to reduce the breakdown risks of semiconductors. Surge voltages and currents are simulated and analyzed based on the classical circuit models of CPPS and railgun. Then, two installation positions of the surgesuppression device are systematically investigated. The simulated results show that installing the surge suppression device at the railgun muzzle can suppress the surge voltages induced by an armature leaving the railgun barrel, and installing the surge suppression device at the railgun breech can reduce overcurrents of semiconductors in reverse recovery phases. Ultimately, experimental results validate the theoretical analysis. [ABSTRACT FROM AUTHOR]

This article deals with the design of an electronic fuse for 380 V dc distribution systems. It has been devised for applications that require current limitation up to 3 A, so approximately 1.2 kW. To protect the main semiconductor against excessive energy dissipation, the tripping time, defined as the time that circuit operates in current-limitation mode, varies with the current fault magnitude, and eventually for very hard fault conditions, i.e., short-circuit, the circuit acts as a circuit-breaker avoiding current-limitation operation. Furthermore, thermal foldback characteristic, defined as the variation of current limitation setpoint with temperature, and tripping time variation with temperature are also considered. Mathematical analysis, circuit design, simulations, and experimental validation have been carried out using a SiC MOSFET as power semiconductor. Experimental results working under different conditions show an excellent performance. [ABSTRACT FROM AUTHOR]

In semiconductor etching processes, fault detection monitors the quality of wafers. However, the detailed dynamics in batch data are ignored in many traditional methods. In this paper, sequential image-based data visualization and fault detection, using bi-kernel t-distributed stochastic neighbor embedding (t-SNE), is proposed for semiconductor etching processes. In the proposed method, multi-modals, multi-phases, and abnormal samples in batches are visualized in two-dimensional maps. First, the batch data are restructured into sequential images and input to a convolutional autoencoder (CAE) to learn the abstract representation. Then, bi-kernel t-SNE is applied to visualize the CAE codes in two-dimensional maps. To reduce the computational burden and overcome the out-of-sample projection diffusion in bi-kernel t-SNE, data subsampling is used in the training procedure. Finally, a one-class support vector machine is employed to calculate the visualization control boundary, and a batch-wise index is presented for fault wafer detection. To demonstrate the feasibility and effectiveness of the proposed method, it was applied to two wafer etching datasets. The results indicate that the proposed method outperforms state-of-the-art methods in data visualization and fault detection. [ABSTRACT FROM AUTHOR]

We introduce and analyze vehicle-allocation algorithms for overhead hoist transport (OHT) systems in semiconductor wafer-fabrication facilities (fabs). OHT is the most widely used type of automated material-handling system in fabs, comprising hundreds of vehicles delivering lots between processing machines. Timely transport unit delivery by OHT systems are critical to the efficient overall operation of a modern fab. We first describe the limitations of current OHT vehicle-allocation algorithms, and then detail an improved system that can be implemented in practical environments to manage the operation of hundreds of OHT vehicles. Our proposed system is based on reinforcement learning. In particular, it uses Q-learning-based dynamic vehicle-allocation algorithms to examine traffic conditions and then allocate an OHT vehicle to a delivery job. We propose multiple algorithms based on the Q-learning approach and compare their performance with that of conventional allocation approaches, which reveals the appropriate algorithms for use in industry. We demonstrate that our algorithms are efficient and sufficiently fast to be used in a practical large-scale setting. [ABSTRACT FROM AUTHOR]

This letter proposes an indirect power dissipation level short circuit protection (IPDL-SCP) method for silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (mosfets). Due to differences between normal conducting and short-circuit (SC) conditions, this method is triggered by the voltage oscillation vss at the parasitic inductance (Lss) of the source and directly monitoring vds of SiC mosfet. For verification, the short circuit protection circuit is tested and proved functional on the SC test bench. Experimental results show that the protection circuit can respond to both hard switching fault (HSF) and fault under load (FUL), while the fastest response delays are 75 ns for HSF and 170 ns for FUL. Comparisons with other commonly used SC protection methods have also been made, which show that the proposed IPDL-SCP method has better performance in shorter protection delays. [ABSTRACT FROM AUTHOR]

We studied nitrogen (N) incorporation effects on the electrical characteristics of SiO2 fabricated by plasma-enhanced atomic layer deposition (PEALD). To determine whether N could be incorporated into the SiO2, nitrous oxide (N2O) plasma with different plasma powers (100, 150, and 200 W) was used during the SiO2 deposition, and the film properties were compared with SiO2 fabricated using a conventional oxygen (O2) plasma reactant. Compared to the O2 plasma reactant, the hard breakdown is improved by 27.5% as N2O plasma power increases up to 150 W, whereas it is degraded at a N2O plasma power of 200 W. These results are found to describe the relationship between the N content and film properties. The N content in the SiO2 films fabricated using increasing N2O plasma power of 100, 150, and 200 W gradually increased by 0.2%, 0.4%, and 0.5%, respectively. However, the N2O plasma power of 200 W results in increased O deficient Si bonding. To investigate the effects of continuous plasma exposure at the bottom layer during the SiO2 deposition, we fabricated indium–zinc oxide (IZO) top-gate bottom-contact (TG-BC) thin-film transistors (TFTs) using the SiO2 as a gate insulator (G.I). Compared to the O2 plasma, the IZO TFTs using N2O plasma reactant during the G.I deposition show stable transfer characteristics. The IZO TFT using N2O plasma with 150-W power during the G.I deposition shows the optimal positive/negative bias temperature stress (P/NBTS) results, with the threshold voltage ($V_{\mathbf {TH}}$) variations of 0.0 and −0.3 V, respectively. [ABSTRACT FROM AUTHOR]

This article introduces a silicon carbide (SiC)-based high-voltage silicon-controlled rectifier (HV-SCR) for on-chip electrostatic discharge (ESD) protection. The SiC HV-SCR is formed by implanting a $\text{p}^{+}$ region into the n-well of SiC laterally diffused metal-oxide semiconductor (LDMOS) structures. Both LDMOS and HV-SCR structures were characterized using a transmission line pulse (TLP) system to investigate their ESD behaviors. The TLP measurement results show that the trigger voltage (${V}_{\text {t1}}$) of the SiC HV-SCR is $\sim 230$ V and has minor dependence on the drift length. The ${V}_{\text {t1}}$ value of the SiC LDMOS decreases from 224 to 202 V when its drift length decreases from 6 to 4 $\mu \text{m}$. TLP measurements with 500- $\Omega $ impedance were conducted to obtain an accurate holding voltage (${V}_{\text {h}}$) and failure current (${I}_{\text {t2}}$) of HV-SCR and LDMOS. Relatively high ${I}_{\text {t2}}$ (i.e., 33 mA/ $\mu \text{m}$) of the HV-SCR structure was observed, which is much stronger than the LDMOS structure (i.e., 0.2 mA/ $\mu \text{m}$). The ${V}_{\text {t1}}$ and ${V}_{\text {h}}$ values of HV-SCR were also investigated with varying gate bias voltages. Moreover, technology computer-aided design (TCAD) simulations of the SiC HV-SCR and LDMOS were carried out to further understand their ESD behaviors. [ABSTRACT FROM AUTHOR]

The reliability of amorphous oxide semiconductor thin-film transistors (AOS-TFTs) is vital for high-definition displays and functional electronic devices. However, drain current drop (DCD) degradation has been commonly observed in the output characteristics of thin-film transistors (TFTs) with channel lengths of ${L} < 10 \mu \text{m}$. Here, we show that DCD is a reversible process that is closely related to reduced metal-oxygen bonds. Based on device theory and simulations, we propose that the DCD effect is mainly caused by hot carriers, whose velocities are inversely proportional to the drain depletion width. Therefore, DCD failure could be alleviated simply by using the drain-offset structure. Experiments show that drain-offset TFTs improve DCD critical voltages (by ~130%) without sacrificing the ON-/ OFF-ratio. These studies provide theoretical and experimental approaches to effectively suppress DCD. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) test standards have been developed based on silicon devices to evaluate the TID response of MOS devices for space use. To estimate the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, 1200 V SiC n-channel MOSFETs from three manufacturers were irradiated with Cobalt-60 $\gamma $ -rays at the high radiation dose rate of 50 rad(Si)/s and the low radiation dose rate of 0.01 rad(Si)/s, respectively. The threshold voltage of devices under test (DUT) shifted toward negative due to the radiation-induced positive oxide trapped charges. Room temperature (RT) anneal of maximum time of 2100 h and high temperature (HT) accelerated anneal of maximum temperature of 105 °C were performed, causing the threshold voltage shift to recover. The synergetic effects of temperature-gate-bias stress and TID on SiC MOSFETs were experimentally studied. In conclusion, the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, and the existing TID test standards are applicable to evaluate the SiC MOSFETs radiation hardness level, but the threshold voltages shift due to HT-gate-bias (HTGB) should be evaluated. [ABSTRACT FROM AUTHOR]

Alterations in the structure of a magnetron, e.g., the A6 relativistic magnetron, are proposed, which considerably increase the device’s build-up speed. We cover the magnetron vane surfaces with semiconductor layers of nonzero electric conductivity, with an exact geometrical design. Semiconductor layers with considerable mechanical strength also provide excellent shielding for the vanes against the high-energy relativistic electrons’ bombardment. The novel structure introduces several new free parameters to the magnetron design procedure and considerably increases the design flexibility. A multistage exact optimization procedure, performed by extensive computer simulations, shows that applying silicon carbide layers with proper geometrical design doubles the build-up speed. In a general trend, we also indicate that adding semiconductor layers with nonzero electric conductivity to the magnetron vanes’ surfaces typically fastens the system by reducing the build-up transient time. It is verified that the insertion of conductivity to the vanes’ bodies with the proper design of shape and depth can increase the mode frequencies, build-up speed, and strength against electrons bombardment, saving the output amplitude. Finally, as shown by the simulation results data, the system behavior is analyzed theoretically. [ABSTRACT FROM AUTHOR]

This article presents a novel concept of a universal solar converter suitable for application in both in the dc or single-phase ac grids using the same terminals. The idea lies in the utilization of the same semiconductors in the dc–dc and in the dc–ac configuration, resulting in minimal redundancy. Possible semiconductor stages are considered. The particular attention is focused on the output filter design along with proper protection circuit selection for dc and ac grids. The design example and comparative analysis between dc–dc, dc–ac, and universal solutions are given. The experimental prototype of the universal solar converter that is rated for 3.6 kVA power in the ac mode and 5 kW in the dc mode is presented. The experimental results demonstrate the ability of operation in ac or dc grids with main correspondent modes. Possible fields of application along with main benefits are addressed in conclusions. [ABSTRACT FROM AUTHOR]

In the semiconductor manufacturing, which consists of significantly precise and diverse unit processes, minute defects can cause significantly large risk, which is directly related to the yield. Through fault detection and classification (FDC), the equipment status is monitored, and the potential causes of faults can be investigated. In the mass production process, unbalanced data problems are also important, including preprocessing methods for data analysis in real time. This study proposes a stepwise FDC method with a process fault detection (FD) and faulty equipment part classification. Fault detection (FD) is proposed using a one-class support vector machine (OC-SVM) to determine anomalies that occur during a process, and fault classification (FC) is followed by the importance between variables that determine whether a fault exists is extracted using extreme gradient boosting (XGBoost). Variables whose importance has been confirmed, are reclassified to a part-level based on the variable name, and defects are notified to the part-level level. An empirical study to validate the proposed data-based framework for fault detection and diagnosis was performed under the scenario of unexpected failure of two ${\mathbf {\mathrm {SF}}}_{\mathbf {6}}/{\mathbf {\mathrm {O}}}_{\mathbf {2}}$ mass flow controllers (MFCs). The experimental results confirmed that the application-oriented proposed framework performed well in FDC operations and showed that it can provide part-level notification to engineers. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing processes, yield analysis aims to increase the yield by determining and managing the causes of low yield. The variable data collected from semiconductor manufacturing processes, in which hundreds of unit processes are implemented according to specific conditions and sequences, are interdependent, and the variables related to previous processes influence the variables in subsequent processes. Therefore, the order of processes should be considered when building a model that searches for the causes of low yield. However, there have been few studies in this area. This paper proposes a low-yield root cause search method considering the order of processes using a long short-term memory with attention mechanism (LSTM-AM) model. Specifically, the LSTM-AM model is applied to data classified according to the process structure of semiconductor products, and the causes of low yield are determined considering the order of processes by extracting attention weights. Experiments are conducted to verify the suitability of the proposed method using real yield data from a semiconductor company. The experimental results confirm that the proposed method outperforms the existing low yield root cause search methods in terms of low yield prediction. [ABSTRACT FROM AUTHOR]

As the critical dimension of transistors has become lower and the stacked layer of semiconductors has become higher, virtual diagnostics to monitor the status of plasma in an etching process has been important because of the reliability of process. In this study, we proposed the model to predict a plasma density of the etch equipment with high accuracy using OES data despite a small number of process conditions. The proposed model could improve the prediction performance of multilayer perceptron by using pre-trained variational auto-encoder as an initializer and had the best performance of several regression methods. At application point of view, it is expected that the model can be used to monitor a plasma density when a wafer is absent from the chamber. Moreover, using the proposed model can more easily understand the status of plasma rather than monitoring thousands of sensor data even without the knowledge about plasma. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor-based products, semiconductor and integrated circuit (IC) design industries have become indicators of global technological advance in this field. As IC structure becomes smaller and smaller, improved process technology and equipment are necessary to maintain and improve wafer yield rates and quality. Among them, the etching technology in the process has a close relationship with the size of IC structure. According to extensive research and analyses put forward by predecessors, the etching process and methods that affect the yield rates and quality of wafers have been well characterized. This study investigates the spray etching method of the single nozzle and double nozzle. Using computational fluid dynamics software developed by Ansys Fluent, the fluid is injected from the center as the starting point at the same flow rate and speed, and according to 2, 4, and 8 seconds of a different cycle and nozzle forms, moving back and forth to supply liquid on the surface of the 300 mm disc. It is assumed that fluid properties do not change with temperature. Additionally, the chemical reaction and thermal reaction of the etching process are not considered. Changes in the surface flow field resulting from different nozzles and cycle conditions are observed. This study involved setting up a set of flow field visualization systems, replacing the etching liquid with colored water, using a digital camera to capture the relationship between the gray index and the thickness of the water film, and calculate the film thickness. The average film thickness deviation (${t}_{avg}$) and variable quantity (${dt}$) were characterized and used as a means to compare performance. The results show that the average film thickness deviation of the double nozzles is higher than the single nozzle, and variable quantity (${dt}$) is lower than that of the single nozzles. In general, the double nozzles increase the thickness and stability of the liquid film thickness on the surface of the disc. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturers use the wafer bin map recognition (WBMR) system to identify failure modes in processing. This study proposes an WBMR system embedded with three modules: data preprocessing, region classification, and systematic pattern recognition. After using a revised Jaccard index to separate random patterns from systematic patterns, we compare three data augmentation techniques, particularly autoencoder-based, to find the best augmented method that addresses any data imbalance problems between the defect classes. We propose an adaptive algorithm to determine the amount of generated data. We describe the two tools, t-distributed stochastic neighbor embedding (t-SNE) and earth mover’s distances (EMD) we use to quantify and visualize the information content of the augmented dataset. Finally, we use an inception architecture of convolutional neural network (CNN) to improve the WBMR system’s recognition accuracy. An empirical study of the semiconductor assembly manufacturer and a public dataset validate that our proposed WBMR system effectively recognizes different types of defective patterns. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. [ABSTRACT FROM AUTHOR]

In this study, abnormal on-current (Ion) degradation in n-type lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) after non-conductive stress (NCS) is investigated. The degradation is caused by electron injection into the insulator layer (IL) during stress. Moreover, Ion degradation reaches saturation within a short time after stress. Experimental data and technology computer aided design (TACD) simulations show that, after NCS, the contact field plate (CFP) induces carriers to inject into the IL above the drift region. It increases the overall on-resistance (Ron) and results in Ion degradation during turn-on. [ABSTRACT FROM AUTHOR]

Three different isolator topologies utilizing photoconductive (PC) elements are explored for their application as a controllable attenuator for a Ka-band radar system. Network analyzer measurements are reported for each geometry in the unilluminated case, while a high-speed, high dynamic range heterodyne detection apparatus is used to measure the transient attenuation behavior of the isolators when illuminated. The electromagnetic characteristics of the illuminated isolators are demonstrated to be in good agreement with COMSOL Multiphysics simulations. Two of the isolator topologies rely on the PC element becoming highly reflective to achieve high isolation, which in turn requires high optical power and charge carrier density (~1017 cm $^{-3}$). For the optical power available here (100 W), the first device demonstrated a peak attenuation of 53 dB, while the second device achieved only 33 dB. In the third topology, RF propagation is parallel to the major dimensions of the PC element. As a result, superior isolation is achieved with the PC element in the primarily absorbing state, associated with significantly lower carrier concentration (~1015 cm $^{-3}$). This device achieved 63 dB of attenuation for only 3 W of optical power, demonstrating that PC technologies may be competitive with other isolator technologies with some notable advantages. [ABSTRACT FROM AUTHOR]

Silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) and SiC/Si cascode devices are two popular normally-off SiC power devices. In terms of the rated voltage and current of a single chip, there are always some SiC/Si cascode counterparts for the SiC MOSFETs. Thus, the two devices can substitute for each other in many fields. However, it is not clear which of the two SiC power devices is more suitable for parallel operation to deal with high current. This article comparatively investigates the paralleling suitability of SiC MOSFETs and SiC/Si cascode devices by theoretical analysis and experimental verifications for the first time. The paralleling suitability of the two devices is quantitatively evaluated by the unbalanced current among paralleled chips under the conditions with asymmetric layout and uneven junction temperature. Both static and dynamic imbalanced current are taken into consideration. Based on the theoretical and experimental results, some design guidelines are proposed to promote current sharing. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

Methanesulfonic acid (MSA) has been widely used in the electroplating step at a backend semiconductor assembly process. This process comes after component encapsulation, which serves primarily to protect internal components of a device as well as to prevent ingression of chemical byproducts. The objective of this article is to study sulfur (S) ingression activities with respect to both electroplating and encapsulation processes and their effect on leadframe surface conditions. This can be achieved through observation of leadframe surface condition on samples prepared through laser ablation or mechanical decapsulation. Results from 17 engineering lots show that 25% of samples analyzed were observed with leadframe surface irregularities. The energy-dispersive X-ray spectroscopy (EDX) analysis confirmed the trace of S element on the area with surface irregularities, which can be linked to S ingression based on the trace of its path from outside, probably due to the existence of a microgap on the package. These findings provide a clearer understanding of the ingression path of S for encapsulated copper (Cu) leadframe. Even though ingression of S does not directly cause a failure, it is thought that this could act as a precursor to further failure mechanisms such as corrosion-like phenomena. [ABSTRACT FROM AUTHOR]

This article proposes a new ripple canceling circuit (RCC) to eliminate the pulsating input current of the conventional flyback converter (CFC). The ripple canceling procedure occurs by two capacitors, one transformer, and a winding, which is added to the CFC transformer core. Besides, the proposed RCC acts as a passive snubber to reduce voltage spikes on the power switch of the converter. In comparison to the similar existing topologies, the proposed RCC does not employ additional semiconductors, and a lower number of magnetic components are used. The proposed RCC is verified by simulation and experimental results. The results show that using the proposed RCC, the input current ripple is reduced to 6% with the minimum power losses. [ABSTRACT FROM AUTHOR]

This research work analyzes the sensitivity of Cylindrical Surrounding Double-Gate (CSDG) MOSFET to process variation using the Poisson equation’s analytical solution. This work has been verified with the numerical simulation. Also, the results obtained have been compared with a multi-gate device known as Cylindrical Surrounding Gate (CSG) MOSFETs. The lightly and heavily doped CSDG MOSFETs have been realized. Their immunity to parameter variation (channel length, Silicon thickness, and Random Dopant Fluctuations (RDFs)) has been compared to CSG MOSFET. This research work indicates that lightly doped CSDG MOSFET exhibits the slightest threshold variations than CSG MOSFETs. It confirms that the lightly doped CSDG MOSFET has better immunity to channel variation than CSG MOSFETs. This is due to its structure and inherent internal and external gate geometry, which offers greater control over the channel. However, RDFs become a dominating factor for heavily doped CSG and CSDG MOSFETs, leading to more dispersion in the threshold variations. Therefore, the CSDG MOSFET’s immunity to channel variation becomes deteriorated due to the larger surface-to-volume ratio. At this point, the CSG MOSFET tends to offer better immunity to process variation. Hence, the sensitivity of threshold voltage to parameter variations depends entirely on the RDFs, as the heavily doped devices are aggressively scaled to the nanometer regime.

The application of organic field-effect transistors (OFETs) in the power device realm has not been explored yet. To achieve a high breakdown voltage, a novel lateral drift region OFET(LDR-OFET) is proposed in this letter. By employing the diketopyrrolopyrrole-based polymer(DPPT-TT) and Poly (methyl methacrylate) (PMMA) to form semiconductor and insulator layers respectively, the fabricated LDR-OFET, despite the simple process and low cost, exhibits an excellent off-state breakdown capability while maintaining a considerable on-state performance. With a $20~\mu \text{m}$ length of the drift region, the LDR-OFET realizes 2200V breakdown voltage on a spin-coated 50nm thick semiconductor layer. The average electric field of the proposed device reaches 1.18MV/cm before an avalanche-like breakdown occurs. The physical nature of the breakdown mechanism is explored using the 1-D PIN equivalent structure and avalanche breakdown theory. The correctness and effectiveness of the proposed LDR-OFET and breakdown analysis are well demonstrated and validated by experimental results. The LDR-OFETs are expected to fill the blank of organic power devices and be the core component of future organic power integrated circuits. [ABSTRACT FROM AUTHOR]

This article proposes a lightweight network called multiscale convolutional neural network with attention (MCNA), which combines a multiscale deep convolutional network with a self-attention mechanism. MCNA identifies ambient gases through signals of semiconductor gas sensor arrays, despite poor selectivity and drift problems. Notably, MCNA extracts temporal features of each signal and relevance among different signals more effectively than deep convolutional networks. MCNA requires much fewer parameters and computation costs than previous deep learning networks, but it still achieves the same high gas identification accuracy; this is crucial for gas sensing embedded systems. When the operating conditions of the gas sensor array change, it also exhibits better generalization ability and identification accuracy. We also discuss the effects of different MCNA architecture parameters and compare MCNA and other baseline approaches. [ABSTRACT FROM AUTHOR]