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In semiconductor substrate fabrication process, copper traces are electroplated on prepreg material to play an important role of communicating signals between functional ICs. In recent years, larger size and high I/O number packages such as HFCBGA, 2.5D and 3D IC were developed, finer copper line width and space (L/S) trace substrate design become more and more important. However, the copper trace broken risk under several thermal manufacturing processes and reliability testing also increasing. A temperature cycling test (TCT) is one of the key experimental testing items for package reliability performance evaluation. The accumulated thermal stress will lead to trace broken risk during test, then the discontinue signal cause function failure. For specific application such as Automotive (ATV), function fail is lethal. Thus, consider risk assessment in the primary structure design stage is essential.In this work, a three-dimensional finite element model is used to evaluate structure design and material selection. In generally, the bilinear casting bulk model was used to evaluate copper trace lifetime performance under thermal cycling test condition. However, this bilinear constitutive model is difficult to simulate long-term creep behavior. Therefore, a new experimental technique was developed to measure the copper trace material properties. The mechanical tensile strength of the thin copper foil was tested with a micro-tester to examine the tensile stress–strain relationship. The copper foil is fabricated to be 18 micron thickness which similar to substrate copper trace thickness. Four kinds of tensile speed (1x100 ~ 1x10-3 mm/minute) at four temperature environments (25rC ~ 150°C) were applied and Stress-Strain (S-S) curves were measured by micro force test system. The tensile result of electroplated copper film shows lower Young’s modulus and higher tensile strength than casting bulk copper.The test vehicle of 11.8 x 11.4 mm2 BGA package which has substrate copper trace crack issue after TCT 1000 cycles (-65°C ~ 150°C) was chosen. Besides, the creep behavior of the copper was taken into account in the simulation model to verify the numerical model and copper’s constitutive model. The copper trace broken risk from the simulation was verified against the experimental data. Additional critical data, such as creep strain energy density (CSED) of the copper trace in the organic substrate and the maximum CSED level location in the substrate layer can be predicted. From the result, reduce the package thermal stress can bring lower CSED on trace, and in this study changed the lower Young’s modulus substrate material to control the thermal stress. The experimental and numerical methods presented here can be used as useful performance evaluation tools to support the choice of suitable package geometry and bill of material (BOM) selection.

Drop test for solder joint reliability is critical for all area arrays and perimeter-leaded surface mount semiconductor devices typically used in handheld electronic products. Joint Electron Device Engineering Council, JEDEC, published a new test standard, JESD22-B111A, to be the revision of the JESD22-B111 for board level drop test in November, 2016. The major differences between JESD22-B111 and JESD22-B111A are PCB size (132×77mm2 to 77×77mm2), PCB layers (8 layers to 10 layers), sample size (15 components/PCB with package size ≦ 15×15 mm2 to 4 components/PCB with package size ≦ 17×17 mm2) and total number of test components (120 components to 48 components). JESD22-B111A also adds the specifications of PCB pad and solder mask opening size for 0.4mm component pitch and 5 lb-in torque value. The component placement on the square board that defined in JESD22-B111A is symmetric so that all of them shall have same stress level during drop test, it is different from the component placement on the rectangular board that defined in JESD22-B111 which results several stress level during drop test. In this paper, board level drop test and simulation followed JESD22-B111 and JESD22-B111A are executed. The simulation result shows conditions follow JESD22-B111A has both smaller normal stress and plastic strain than conditions follow JESD22-B111; drop test experiment result shows JESD22-B111A has longer characteristic life, too. The study of package surface mount placement orientation for rectangular package under JESD22-B111A condition is also executed by simulation, due to it is not defined in the new revised standard. The simulation result shows circumferential oriented component placement has larger plastic strain and radial oriented component placement has larger normal stress, it means the former ease to have solder fracturing failure mode and the latter ease to have intermetallic compound layers fracturing failure mode.

Global measurements of upper tropospheric/lower-stratospheric water vapor and ice particle size distribution in clouds are critically needed to reduce uncertainties in global weather and climate models. To address this need, the conically scanning Tropospheric Water and Cloud ICE (TWICE) millimeter and submillimeter radiometer instrument is being developed. A low-noise, power-efficient command and data handling (C&DH) subsystem has been designed to control TWICE data acquisition and other subsystems. The C&DH prototype board meets functional, noise and size, weight and power (SWaP) requirements for deployment in a 6U-class satellite. Considering the limited power resources available on such platforms, a highly-efficient power regulation board has been designed to minimize power losses and reduce system noise. Furthermore, all of the components have been tested for radiation tolerance in low-Earth orbit.

Global measurements of cloud ice particle size, total ice water content and water vapor content in the upper troposphere are critically needed to improve knowledge of the role of ice clouds in Earth's climate, precipitation and cloud processes. Such observations will enable improvement in cloud and moisture simulations in global climate models as well as precipitation forecasts on a global basis. Measurements at a range of frequencies in the millimeter- and submillimeter-wave frequency range provide sensitivity to ice particle size distribution in the range of tens to hundreds of micrometers. To perform this measurement on a global basis, a new millimeter- and submillimeter-wave instrument is currently under development with suitable mass, power and volume to be deployed on 6U-Class nanosatellites. To achieve miniaturized receivers in this frequency range, InP MMIC technology has been scaled to 25-nm gate length transistors, enabling demonstration of low-noise amplifiers with sufficient gain at frequencies up to 1 THz. This technology is being applied to develop direct-detection submillimeter-wave receivers at 240 GHz, 310 GHz and 670 GHz. InP MMIC technology has also enabled multipliers for local oscillators and subharmonic mixers for temperature and humidity sounding channels near atmospheric absorption lines at 118.75, 183.31 and 380.20 GHz.

In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is evaluated by the most recent commercial tool and has an average deviation of 6.5% with 242× speed up. Our placer can reach the same quality compared to Capo and APlace2 with 2–3× speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. To the best of our knowledge, this is the first thermal-aware placer using analytical thermal model and experimented on large scale design. It takes 6.5 hours to complete entire 2005 ISPD benchmark using our thermal aware placer.