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New / Old JEDEC board level drop reliability test standards evaluation: Measurement and simulation study

Authors :
Ian Hu
Ryan Chen
Janae Ho
Ming-Han Wang
Sean Shih
Sarah Lee
Source :
2017 IEEE CPMT Symposium Japan (ICSJ).
Publication Year :
2017
Publisher :
IEEE, 2017.

Abstract

Drop test for solder joint reliability is critical for all area arrays and perimeter-leaded surface mount semiconductor devices typically used in handheld electronic products. Joint Electron Device Engineering Council, JEDEC, published a new test standard, JESD22-B111A, to be the revision of the JESD22-B111 for board level drop test in November, 2016. The major differences between JESD22-B111 and JESD22-B111A are PCB size (132×77mm2 to 77×77mm2), PCB layers (8 layers to 10 layers), sample size (15 components/PCB with package size ≦ 15×15 mm2 to 4 components/PCB with package size ≦ 17×17 mm2) and total number of test components (120 components to 48 components). JESD22-B111A also adds the specifications of PCB pad and solder mask opening size for 0.4mm component pitch and 5 lb-in torque value. The component placement on the square board that defined in JESD22-B111A is symmetric so that all of them shall have same stress level during drop test, it is different from the component placement on the rectangular board that defined in JESD22-B111 which results several stress level during drop test. In this paper, board level drop test and simulation followed JESD22-B111 and JESD22-B111A are executed. The simulation result shows conditions follow JESD22-B111A has both smaller normal stress and plastic strain than conditions follow JESD22-B111; drop test experiment result shows JESD22-B111A has longer characteristic life, too. The study of package surface mount placement orientation for rectangular package under JESD22-B111A condition is also executed by simulation, due to it is not defined in the new revised standard. The simulation result shows circumferential oriented component placement has larger plastic strain and radial oriented component placement has larger normal stress, it means the former ease to have solder fracturing failure mode and the latter ease to have intermetallic compound layers fracturing failure mode.

Details

Database :
OpenAIRE
Journal :
2017 IEEE CPMT Symposium Japan (ICSJ)
Accession number :
edsair.doi...........98a236039212221a7d1b05d8731fa26d
Full Text :
https://doi.org/10.1109/icsj.2017.8240119