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This paper presents the calibration of the novel kinetic velocity model (KVM) in the drift-diffusion (DD) transport approach, which can account for the ballistic effect in short-channel devices. The KVM considers a thermionic emission limit and a free carrier acceleration limit for the mobility. We develop a methodology to extract the parameters for the KVM and for the high-field saturation velocity model for SiGe nanowires over the whole mole fraction range. The calibrated DD simulations with KVM show good agreement with Boltzmann transport equation results in terms of on-state current and carrier-weighted velocity distribution over a wide range of gate lengths for both linear and saturation regimes.

In this paper, the influences of channel transport on the output characteristic in sub-100nm heterojunction tunnel FET have been investigated through TCAD simulation. The calibrated tunneling and transport parameters with experiment have been adopted. The influences of the parameters characterizing channel transport, i.e., mobility, channel length, and saturation velocity, are analyzed in detail under different biases. It is found that the channel transport has stronger impact on the performance of the device biased in the linear region and with smaller mobility, longer channel, and higher saturation velocity. The saturation drain voltage can be reduced by improving the mobility and reducing the saturation velocity. However, the latter will reduce the current simultaneously. What’s more, considering quantum confinement, the variation in performance of the device induced by the change of mobility is still visible after some optimization strategies are used.

This paper discusses different parameters and their effects on the efficiency of a crystalline solar cell. This is done using a 1D Drift Diffusion model for silicon solar cells by varying several parameters like the n-layer and p-layer thickness, electron and hole doping concentration, the electron and hole maximum SRH lifetime, and electron-hole saturation velocity. A various permutation of the values of these parameters was used to study various characteristics of the solar cell and calculate the maximum efficiency. It investigated various output characteristics to understand the correlation between these input parameters and the efficiency of solar cells. Simulating graphs such as current and power vs voltage, band diagrams helped us in getting optimum input parameters to achieve maximum efficiency. The paper presents, as motivation for this work, a number of parameters that can be used to increase the efficiency of a solar cell, which is a fundamental unit of a solar panel, which in turn can be a stepping stone to move towards a cleaner energy source. The efficiency of the solar cell peaked when the n-layer and p-layer thickness took $3\ \mu \mathrm{m}$ and $55\ \mu \mathrm{m}$ values respectively, while the ideal SRH lifetime for a crystalline silicon solar cell was measured to be 10−2 s. The efficiency achieved for the same was 24.61%. This paper further explores and understands the reasons for these optimums and how and by how much they improve the efficiency of the solar cell.

A drain current model based on Lambert W function is analyzed for lightly doped (undoped) short channel tri gate FinFET (TG-FinFET). The channel length modulation (CLM), the effect of series resistance, mobility degradation and saturation velocity are included in the drain current model. Quantum mechanical effect (QME) is also included to achieve precise drain current for such a small channel device. The model is inspected mainly for two fin widths with two dielectric materials namely, silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ). A complete study of electrical parameters including surface potential and the threshold voltage are addressed for both the dielectric materials. The threshold voltage is cross-examined by reported experimental results.

Gallium nitride (GaN) high-electron-mobility transistor (HEMT) and vertical GaN metal-oxide-semiconductor (MOS) devices have potential application to high power and high frequency because of their superior characteristics, such as wide band gap (B g ), high electron saturation velocity, and a high critical breakdown voltage [ 1 – 3 ]. Gate insulator plays an important role to suppress the leakage current in both GaN HEMT and GaN MOS devices. Various materials such as SiO 2 , Al 2 O 3 , HfO 2 , AlSiO x , and HfSiO x have been widely investigated as gate insulator, and films of these materials are typically deposited via chemical vapor deposition or atomic layer deposition (ALD) [ 4 – 10 ]. Figure 1 shows the relationship between dielectric constant ( k ) and B g of candidate gate insulators [11] . The B g generally decreases as the k value increases. HfO 2 is known to have a high k value but crystallization temperature is as low as 400°C. Al 2 O 3 starts to crystalize around 700°C. On the other hand, silicate materials such as AlSiO x and HfSiO x have a more stable amorphous structure at 800°C and expect to suppress the leakage current. Here, AlSiO x and HfSiO x films were formed by a two-step process such as film formation of (Al 2 O 3 ) m /(SiO 2 ) n and (HfO 2 ) m /(SiO 2 ) n nanolaminate structures using ALD, respectively, and post-deposition annealing (PDA) treatment.

Since the two dimensional (2D) material are found to have potential for transistor application due to their suppression in short channel effect, they have attracted significant attention from worldwide researchers, and gradually demonstrate the potential for the next-generation transistors. In all of 2D materials, transition metal dichalcogenide (TMD) monolayers are the most popular ones because they have wider bandgap to provide better on/off ratio, and also have good mobility in theoretical prediction [1] . In recent years, there are some groups using TMD monolayers to make transistors and getting on/off ratio larger than 10 7 [2] . However, due to difficulties to grow perfect 2D monolayer, mobility reported by experiments is much lower than the theoretical prediction. The real intrinsic transport properties of TMD materials are still unclear. As a result, it is needed to be further discussed. There are several ways to calculate mobility. One common way is Boltzmann transport equation. Another way is Monte Carlo approach, which can simulate the movement of carriers in materials. It can calculate the velocity under different electric fields and also saturation velocity. As transistors get smaller, besides low-field mobility, high-field velocity becomes more critical. As a result, in this work, Monte Carlo method is adopted to simulate transport of electrons in monolayer MoS 2 and WS2 2 . We will discuss the electron velocity under different electric fields and also discuss the influence of satellite Q valleys on electron transport in both TMD materials.

GaN-based HEMTs are attractive devices for RF, microwave, and millimeter-wave applications, with excellent power and noise figure performance having been demonstrated. Recently, graded-channel structures have been explored for their potential to improve linearity through channel engineering. However, due to the longitudinal optical (LO) phonon coupling in III-N structures, graded channel devices are also seen to exhibit improved carrier saturation velocity over a wider range of device bias conditions. In turn, this may enable RF performance improvements. We report the first study of bias dependence of millimeter-wave RF performance for graded-channel GaN-based HEMTs. In contrast to conventional abrupt AlGaN/GaN heterostructure HEMTs, the higher carrier velocity leads to high f t and f max over a wide range of bias conditions. This has implications for the design of high-linearity and power-efficient amplifiers.

Recently, due to its potential in high-speed flexible electronics, radio-frequency transistors based on two-dimensional MoS 2 has attracted the interest of researchers. However, for the moment, little is known on the RF performance of MoS 2 transistors at cryogenic temperatures, which is important for evaluating performance limits of high-frequency MoS 2 devices. In this work, we report the RF performance of MoS 2 transistors at cryogenic temperatures based on chemical vapor deposited bilayer MoS 2 for the first time. As the temperature reduces, the higher cut-off frequency was achieved. At the liquid helium temperature, extrinsic and intrinsic $f_{\mathrm{T}}$ of 5.7 and 12.7 GHz for the transistor with 300 nm gate-length were achieved. Furthermore, saturation velocity and intrinsic $f_{\max}$ of 2.4×106 cm/s and 24 GHz were obtained at 4.3 K, respectively. The revealed high-frequency performances of MoS 2 transistors at cryogenic temperatures are helpful to the advancement of MoS 2 high-frequency electronics.

In this paper, two- 2DEG channels of AlGaN/GaN HEMT are created with Common Drain on a single GaN substrate for improving high power performance of the device. The results obtained for Common Drain Dual HEMT (CDDHEMT) have been compared with conventional HEMT. The results obtained for CDD-HEMT show higher drain current, current gain, cut-off frequency and transconductance. Drain current of CDD-HEMT is three times greater than conventional HEMT. Transconductance is three times higher in comparasion to conventional HEMT. CDD-HEMT has potential applications in high power high frequency domain.

The influence of an accurate electron velocity-field relationship modelling on pulsed IV and small-signal RF characteristics in GaN-on-Si HEMTs is discussed and compared to measurements. We show by technology computer-aided design (TCAD) simulation and measurements that not only the lowfield mobility and saturation velocity are of great importance, but also the transition behaviour in between has to be modelled accurately. Experimentally, we extract the velocity-field relationship using device simulation and measured data with ultra short pulse lengths. To the best of our knowledge, this is the first study on the velocity-field relationship in GaN-on-Si devices.

We report on GaN-based field effect transistors with laterally-gated multiple 2DEG channels, called BRIDGE FETs (buried dual gate FETs). Unique operation principle of the transistors demonstrated unprecedented device characteristics suitable for efficient and linear millimeter-wave power amplifier applications. Multiple 2DEG channels formed in AlGaN/GaN and AlN/GaN material systems are compatible with the BRIDE FET structure, adding design flexibility for an increased drain current density with higher frequency performance. The BRIDGE FET fabricated on a 4-channel epi structure with a net 2DEG density of 1.2×1013 cm-2 exhibited 1.7× higher saturation current density than those on a single-channel with the same 2DEG density. This is attributed to a higher saturation velocity of 2DEG with a lower density per channel. Finally, hexagonal micro-scale device cells consisting of segmented BRIDGE FETs construct a power amplifier (PA) unit cell, where distributing heat sources uniformly over an entire PA cell area maximizes its area power density while minimizing a rise of the peak junction temperature.

AlGaN channel transistors are promising candidates for high power RF transistors due to their superior material properties. The larger breakdown field and similar saturation velocity compared to GaN make AlGaN channel transistors potentially capable of delivering higher power density at high frequencies. So far the highest reported $\mathrm{f}_{\mathrm{T}}$ is 28 GHz on Al 0.85 Ga 0.15 N/Al 0.70 Ga 0.30 N transistors with RF power density of 0.3 W/mm at 3 GHz [1]. The major obstacle to achieve high RF performance is the challenge to form good ohmic contacts to Al-rich AlGaN. Here, we show significantly better small and large signal RF performance than what have been reported on high Al-composition AlGaN transistors with regrown side contacts.

This abstract presents an experimental study on the measurement of the hole impact ionization coefficient and saturation velocity in GaN. A novel p-n structure with a buried p-GaN was designed and demonstrated to have avalanche capability. Ultraviolet generated holes were swept into the high electric field region when the p-n diode was reversely biased and triggered the hole-initiated impact ionization multiplication. The measured hole saturation velocity is $7\times 10^{6}$ cm/s, and the impact ionization coefficient is $\boldsymbol{\beta}(\boldsymbol{E})=4.39\times 10^{6}\mathbf{exp}(-1.8\times 10^{7}/\boldsymbol{E})$ .

In this work an average channel temperature of power InAIN/GaN HEMT prepared on SiC substrate has been investigated using quasi-static 1-V characterization. The analysis of drain current change depending on source resistance, threshold voltage and saturation velocity drop was utilized and used for temperature versus dissipated power calculations in differential form. The source resistance and threshold voltage were determined experimentally by measurements of output and transfer characteristics at different ambient temperatures whereas saturation velocity relative drop was used from available resources. Obtained results were compared with simulations.

We propose a simple method for incorporating the virtual gate effect present in Aluminum Gallium Nitride (AlGaN) / Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) in numerical simulation of their ON-state current-voltage characteristics. Further, we show that the simulations which match the measured ON-state data neglecting the virtual gate effect end up employing an electron saturation velocity versus gate bias behavior that is qualitatively unphysical.

High aluminum content AIGaN channel high electron mobility transistors (HEMTs) are an attractive candidate for the next generation of RF and high-power applications amongst ultra-wide bandgap materials $(\mathrm{E}_{\mathrm{G}} > 3.4\mathrm{eV})$ . This is due to numerous beneficial intrinsic material properties, such as high saturation velocity and large critical electric field. The built-in polarization electric field populates the 2-dimensional electron gas (2DEG) which cannot be depleted entirely at zero bias by the Schottky contact for a reasonable barrier thickness. As was observed in GaN channel HEMTs, these AIGaN channel devices intrinsically operate as depletion mode (d-mode). While d-mode devices are preferable for RF applications, high power applications typically require enhancement mode (e-mode) operation in order to guarantee system reliability [1]. Through the use of a $\mathrm{p}-\mathrm{Al}_{0.3}\mathrm{Ga}_{0.7}\mathrm{N}$ gate on an AIGaN channel HEMT, this work shows the capability to achieve enhancement-mode operation with a +0.3V threshold voltage, high saturated drain current $(> 60\mathrm{mA}/\mathrm{mm})$ , no gate hysteresis $(\Delta \mathrm{V} , and exceptionally low gate leakage current of $ even under high forward bias of $\mathrm{V}_{\mathrm{GS}}=8\mathrm{V}$ .

In this paper, we report state-of-the-art large area CVD monolayer MoS2-based RF transistors and RF switches. An embedded gate structure was used to fabricate short channel CVD Mos2Rf FETs with an intrinsic f T of 20 GHz, intrinsic $\mathbf{f}_{\mathbf{max}}$ of 11.4 GHz, and the high-field saturation velocity V sat of $\mathbf{1.88}\times \mathbf{10}^{\mathbf{6}}\ \mathbf{cm}/\mathbf{s}$ . The gate-first process allows for enhancement mode operation, $\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$ ratio of $\mathbf{10}^{\mathbf{8}}$ , and a transconductance $(\mathbf{g}_{\mathbf{m}})$ of 70 $\pmb{\mu} \mathbf{S}/\pmb{\mu}\mathbf{m}$ . Also, we use a vertical MIM structure for a RF switch based on CVD Mos2. The device was programmed with a voltage as low as 1 V, and achieves an ON-state resistance of $\sim \mathbf{5}\ \pmb{\Omega}$ and an OFF-state capacitance of ~6 fF. We measured and simulated the RF performance of the device up to 50 GHz and report 0.5 dB insertion loss, 15 dB isolation (both at 50 GHz), and 5 THz cutoff frequency.

InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies $(f_{max})$ above 1THz under low collector voltage due to electron velocity overshoot in the InP drift collector [1] [2]. Under higher collector voltage, however, a quick onset of $\Gamma-\mathrm{L}$ scattering limits the average electron velocity to the saturation velocity (Fig. 1(a)-(c)), leading to a Johnson's figure-of-merit (JFOM) second to GaN HEMTs and a limited transistor power bandwidth for InP DHBTs [3]. Here we propose a velocity-engineered device structure called the segmented-collector DHBT (SC-DHBT) that incorporates p-type scattering layers within the drift collector to reduce the electron kinetic energy and force a greater electron distribution into the low effective mass $\Gamma-$ valley for extended velocity overshoot (Fig. 3(a)). Transport simulations show the collector transit time $\tau_{c}$ is reduced from 1.23ps in the reference design to 0.90ps in a double scatterer design at $V_{cb}=5\mathrm{V}, J_{c}{=}$ 1mA/um2. The proposed SC-DHBT design is suited for large power bandwidth power amplifiers.

Power electronics switching devices involving Wide Band Gap (WBG) materials such as, silicon carbide (SiC) and gallium nitride (GaN) provide substantial switching level improvements as compared to the silicon (Si) devices. Their ability to operate at higher voltages, temperatures and frequencies make them highly eligible for use in the future power electronics. In order to provide a comparative analysis of these materials, we studied their various parameters like energy band gap, carrier mobility, saturation velocity and thermal conductivity. A study also has been conducted to analyze and evaluate performance of GaN FET, SiC JFET and Si IGBT based dc-dc buck boost converter. Switching performance and energy dissipation at a variable junction temperature range is compared and evaluated for three power devices. Transistors' switching and conduction losses and their temperature dependency is discussed at the end. The results show that GaN based converter has better switching performance and overall efficiency, but have strong dependency of temperature.

For the first time, RTN measurement is utilized to measure the temperature (T) distribution along the channel, induced by Self-heating effect(SHE). The results have shown that the channel temperature of 14nm pFinFET is 170K higher than that of nFinFET as a result of the difficulty of heat dissipation in eSiGe S/D of pFinFET. This has been justified by a Spice built-in model to extract the necessary parameters. In nFinFET, although S/D series resistance (R sd ) dominates at room T, the channel resistance (R c ) is larger than R sd at a higher T because of degradation of saturation velocity caused by SHE. On the other hand, in pFinFET, R c dominates at low and high T, and R sd becomes significant at high T because of embedded high thermal-resistance material, SiGe, in S/D. This has been justified by the mobility reduction due to the increment of phonon scattering induced by SHE. Finally, the impact of SHE on the shrinking of SRAM signal-to-noise ratio has been used as a benchmark test. New findings provide valuable information on the understanding of SHE-resistant design of future generation FinFET devices.

Both Carbon Nanotube and Silicon Nanowire are emerging as promising materials for the development of next generation electronic devices. Our focus is mainly on the comparative study of Silicon Nanowire Field Effect Transistor (SiNW-FET) and Carbon Nanotube Field Effect Transistor (CNT-FET). In this work, we have simulated an n-type single walled CNT-FET and a SiNW-FET. A brief comparison between the transconductances of both types of devices due to the applied strain has been studied where SiNW-FET shows incremental change in transconductance which happens to decrease for CNT-FET for lower input voltage range. Afterwards, we have observed the velocity vs applied electric field curves for both CNT-FET and SiNW-FET. It has been shown that although SiNW-FET has lower saturation velocity than CNT-FET, it can be improved by applying tensile strain. Finally, the direct tunneling gate leakage currents for CNT-FET and SiNW-FET have been investigated, where CNT-FET has been proved to be a better choice for gate leakage reduction.

It is shown that the free charge carrier capture-emission process causes both the charge carrier density and mobility fluctuations. In this report we present the calculation results in order to find out how the capture-emission process affects the free charge carrier mobility, and how the latter impacts the low-frequency noise level. The carrier mobility dependence on phonon, impurity and carrier-carrier scatterings and mobility change dependence on the electric field were taken into account. It is also shown that fluctuations of the charge carrier density and mobility due capture-emission process are completely correlated, and that their relaxation times are the same as for charge capture-emission process. The general expression for estimation of active capture center density in the sample from the low-frequency noise measurements is presented.

We report on chemical vapor deposited (CVD) M0S2 radio frequency (RF) transistors with a record fT of 20 GHz and fmax of 11.4 GHz, and the largest high-field saturation velocity, Vsat = 1.88 × 106 cm/s, in MoS2 reported so far. The gate-first approach, facilitated by cm-scale CVD MoS2, offers enhancement mode operation, Ion/Ioff ratio of 108, and the highest reported transconductance (gm) of 70 μS/μm. The intrinsic ft (fmax) obtained here is 3X (2X) greater than previously reported top-gated CVD MoS2 RF FETs. With as-measured S-parameters, we demonstrate the design of a GHz MoS2-based RF amplifier. This amplifier has gain greater than 15 dB at 1.2 GHz, input return loss > 10 dB, bandwidth > 200 MHz, and DC power consumption of ∼10 mW.

DC characteristics of AlGaN/GaN on Si MOS-HEMTs are measured and numerically simulated, with substrate temperature up to 140°C, varying the gate width and gate length. Different gate recess depths are simulated in ATLAS in order to further investigate and optimize the device performance. Thermal boundary conditions and device thermal resistance are included in the structure for accurate simulation of the heating response. In addition, the relationship of the threshold voltage and saturation velocity with the substrate temperature and gate width has been studied and set in order to ease the modelling of these devices.

We report Multi-Valley-Multi-Subband Monte Carlo simulations of the velocity-field curves in bulk and thin film InAs, GaAs and In 0.53 Ga 0.47 As. Our model suggests that surface roughness scattering reduces the saturation velocity of nanometer-scale films significantly below the corresponding Silicon value. The injection velocity, instead, remains larger than for Silicon down to small film thickness. The results provide a useful reference for the calibration of TCAD compact models for thin films of In x Ga( 1−x )As compound semiconductors of interest for future CMOS technology nodes.

In this work we demonstrate state-of-the-art large area monolayer CVD M0S2 based RF transistors on both flexible and Si substrates. We report the highest RF performance (fT ∼ 5.9GHz and fmax ∼ 3.3GHz) among flexible MoS2 based thin film transistors. Our embedded gate CVD MoS2 transistors on CMOS compatible Si substrates shows record fT∼ 20GHz, fmax ∼ 11.4GHz, and saturation velocity vsat ∼ 1.88∗106 cm/s. We also present the design of MoS2 based RF circuits (GHz amplifier and flexible wireless AM receiver).

We present atomistic calculations of the band structure and the phonon-limited carrier transport properties of zigzag graphene nanoribbons. We show that a lateral electric field can be used to tune the carrier mobility and mean free path over orders of magnitude and to change the spin polarization of the current. These effects could be nicely exploited in electronic and spintronic devices.

In the neoteric years, Graphene is one of the predominant resplendence in the horizon of fabrication technology owing to some of its tremendous electronic properties like zero band gap, high saturation velocity, higher electrical conductivity and so on. Graphene based devices are now being deliberated as one of possible options for post Si based electronics era. In this paper, we have analyzed the miscellaneous idiosyncratics of top gated graphene metal oxide semiconductor field effect transistor (MOSFET). Surface potential dependent quantum capacitance is obtained self-consistently along with linear and square root approximation. Gate voltage dependence of surface potential has been shown. Output characteristics, transfer characteristics of the proposed device model have been investigated. Considering all of the graphical illustrations, we strongly recommend Graphene to be a fellow replacement of silicon based devices in future MOSFET applications.

It is known that cubic silicon carbide (3C-SiC) differs from other SiC polytypes in the highest electron mobility (1200 cm2/(V s)) [1], which is independent of the crystallographic direction. The rest of the SiC parameters (critical electric field, maximum working temperatures, electron saturation velocity, heat conductivity) differ from the parameters of the hexagonal polytypes only slightly [2]. Thus, 3C-SiC is a rather promising material for development of various kinds of semiconductor devices.

From small voltage regulators to large motor drives, power electronics play a very important role in present day technology. The power electronics market is currently dominated by silicon based devices. However due to inherent limitations of silicon material they are approaching thermal limit in terms of high power and high temperature operation. Performance can only be improved with the development of new power devices with better material properties. Silicon Carbide devices are now gaining popularity as next generation semiconductor devices. Due to its inherent material properties such as high breakdown field, wide band gap, high electron saturation velocity, and high thermal conductivity, they serve as a better alternative to the silicon counterparts. Here an attempt is made to study the unique properties of SiC MOSFET and requirements for designing a gate drive circuit for the same. The switching characteristics of SCH2080KE are analyzed using LTspice by performing double pulse test. Also driver circuit is designed for SiC MOSFET SCH2080KE and its performance is tested by implementing a buck converter.

Recently, based on our successful exhibition of charge packets phenomenon under a series of electric field intensity (ranges from 10 kV/mm to 50 kV/mm) in LLDPE thin films (500 µm), the retrival of real charge carrier mobility was attempted to work out using numerical methods. To make the migration of charge packets in both numerical simulations and experimental measurements incline to unanimous, a slightly adjusted bipolar charge transport model was adopted for charge packet simulations and a preset electric field-charge migration speed carve was tuned during the iterative simulations. Results show that simulation using this model is qualified for the charge packet reproduction. The simulated charge distribution is more precise than that in former research, and verification simulations basing on the final retrieved carrier mobility carve suit well with the measurement results.

In the past two decades, the GaN-based high-electron-mobility-transistor (HEMT) has attracted tremendous attentions due to its wide bandgap, high electron mobility and high electron saturation velocity, which makes it a good candidate in the area of high frequency and high power applications [1]-[5]. However, there are still some issues such as high density of surface states and high gate leakage current, which hinder the final performance and reliability of the devices. Although GaN metal-oxide-semiconductor HEMT (MOSHEMT) with a thin amorphous gate dielectric is studied as an effective way to suppress gate leakage current and passivate the surface[6], high-quality gate dielectric on GaN and deep understanding of GaN MOS structures are still lacking and need to be developed. In this work, we have successfully integrated an atomic layer epitaxy (ALE) single crystalline MgCaO [7] as gate dielectric with unprecedented high-quality interface in AlGaN/GaN MOSHEMT on SiC substrate and demonstrated low gate leakage current (I g ), high drain current (I D ), high on/off ratio, small current collapse, and good RF performances with a deep sub-micron T-gate beyond the previous work on AlInN/GaN structure [8].

There is a growing interest in the design of novel flexible electronics for future internet of things (IoT) systems [1]. IoT requires design of low power RF electronics operating at GHz frequency range. Molybdenum disulphide (MoS2) is the prototypical transitional metal dichalcogenide (TMD) affording a large semiconducting bandgap (1.8eV), high saturation velocity, good mechanical strength, high mobility (> 50cm2/Vs), high on/off ratio (> 106), good current saturation and GHz RF performance [2]. In this work, we demonstrate wafer scale monolayer MoS 2 based flexible RF nanoelectronics that can be used for low power nanoelectronics and flexible IoT systems.

Self-heating effects of sub-20-nm fin-shaped FET (FinFET) technologies are studied and analyzed in this work using well-calibrated TCAD 3-D electro thermal simulations. We show that the thermal performance characteristics can be accurately measured from the ac capacitance method using simple extraction techniques. The extracted thermal time constants are in nanoseconds range, and show a decrease with scaling. This is because of the increase in the surface area to volume ratio of the fins in FinFETs. The thermal resistance decreases with increase in the input power owing to the spread of the heated volume. Bulk FinFETs have a less thermal resistance as compared with SOI FinFETs because of the effectiveness of its lower fin region. Thermal resistance increases with reduction in fin pitch and increase in the number of fins. Drain current degradation because of self-heating effects, decreases with scaling. This is because the threshold voltage dependence on temperature dominates the mobility or saturation velocity dependence.

This article presents a DC model for graphene field effect transistor with improved accuracy for wireless communications. The model takes into account the mobility difference between electron and hole, accurately modelling the carrier transport in the graphene channel. In addition, the variations of mobility against carrier density is also included in this model. Excellent agreement has been achieved between the modelled results and measurement data.

The superior material properties such as higher breakdown field, thermal conductivity and wider bandgap make Silicon Carbide (SiC) appropriate for transistor applications. However, there are certain parameters where SiC have yet to achieve required performance levels. SiC have number of polytypes having mature technology. Being one of the SiC polytypes, 3C-SiC has higher mobility and saturation velocity. This paper presents symmetric 3C-SiC Double Gate MOSFET (DG MOSFET) and asymmetric 3C-SiC DG MOSFET. The two designs were simulated for different applied voltage at various lengths. From simulated results it can be seen that asymmetric 3C-SiC DG MOSFET shows increment in on-current values and decrement in off-current values for 22 nm, 40 nm and 60 nm channel length.