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Large-capacity DC/DC converter with high-input voltage and low-output voltage generally has a serial-input parallel-output structure with several stages for efficiency and miniaturization. However, error values in active and passive elements in the power supply unit of a multi-stage DC/DC converter causes a power imbalance in each terminal. This degrades the reliability of the DC/DC converter because of both the increase in stress on elements and excessive heat. Therefore, this study proposes a method to solve this problem by using multiple input transformers that share magnetic coupling to improve the power imbalance of a DC/DC convert at each level.

Present study analyzed the efficiency characteristics of LLC converters having current doubler rectification circuits. A current doubler rectification circuit has a coupled inductor as rectification circuit on the secondary side output terminal of the converter. A current doubler rectification circuit generally requires inductors on the secondary side however, the characteristic of an LLC converter preclude the inclusion of inductors on its secondary side. This problem is resolved here by proposing, a circuit system that has very small inductance values and uses a coupled inductor on the secondary side output terminal. The proposed circuit system is advantageous compared to center tap systems typically used at present, as confirmed by analysis and verified through simulated analysis.

FLIM is relatively stable about photo-bleaching effect. In case of dye lias multi-exponential decay property, fluorescence lifetime can be affected by photo-bleaching. Such lifetime variation can cause critical error in many FLIM applications. If lifetime is changed by photo-bleaching, we can't measure accurately donor lifetime with acceptor. It is difficult to separate lifetime variation by photo-bleaching and FRET. For this reason we carry out the experiment to know influence of such fluorescence intensity loss on fluorescence lifetime.

Power control is important in the operation of dc microgrid, particularly for the power sharing between different types of power sources including PV, wind power generation systems. In this paper, an effective control scheme for dc microgrid with energy storage system (ESS) is proposed. The power sharing scheme using two ESSs in a dc microgrid for stable operation is proposed. Detailed effective control scheme of voltage and power control is described. To verify the performances of the proposed effective control scheme, the simulation analysis using PSCAD/EMTDC is conducted. The results demonstrate the effectiveness of the control scheme that can improve power balancing and sharing in connection with ESSs for stable operation of dc microgrid under various generation and load conditions.

The power systems have encountered with a problem such as unbalance current due to loads unbalance. Particularly, the problem rises in the small scale grid such as a microgrid that is installed in remote country and island which are difficult to reach existing power grid. To solve the unbalance current of the grid, we usually use compensators for balancing the current of the grid. In this paper, the authors propose a power conditioning system (PCS) using energy storage system which has not only normal operation functions but also a compensation function of the unbalance current of the grid without special compensators. The proposed PCS is modeled and simulated using PSCAD/EMTDC to demonstrate the effectiveness of the system.

This paper analyses a three-phase four-leg voltage sourced inverter (VSI) based load unbalance compensator (LUC) including its control algorithm, which is a component of a microgrid. The purpose of proposed three-phase four-leg VSI based LUC is to improve power quality of the stand-alone microgrid. Power quality of the microgrid which was installed in Mara-island, Korea is analysed using a real operational data. In this work, the microgrid in Mara-island which includes a photovoltaic power generation system, a diesel generator, a battery energy storage system, and a power management system is modelled in PSCAD/EMTDC, and proposed three-phase four-leg VSI based LUC is also modelled and applies to the microgrid. Power flow and stability of the modelled microgrid with the LUC is analysed under variable irradiance and unbalance loads. The results show that the proposed LUC helps to improve stability of the stand-alone microgrid. The proposed three-phase four-leg VSI based LUC and its control algorithm can be effectively utilized to the stand alone microgrid which has large unbalance loads.

In this paper, LLC series resonant converter with current-doubler as a rectification circuit for secondary side is proposed. The current-doubler circuit is generally used for the high voltage input and low voltage output application to get high efficiency characteristics with reduced transformer turn ratio. However, an inductive circuit is not used in a secondary side for the LLC series resonant converter generally. When there is inductive circuit like current-double on the secondary side, the resonant characteristics are changed. In this paper, LLC converter with the current-doubler using coupled inductor is proposed. We verify that the secondary side current-doubler using coupled inductor is not affect to the resonant characteristic of primary LLC by the mathematical analysis. Finally, the analysis results are proved by the simulation and experiments.

DC HTS power cable has drawn attention as an ideal solution for transmitting massive electric power for long distances. As one of the accessories of the DC HTS power cable, the stop joint box (SJB) is an essential component for long distance transmission cable connections and separation of the cooling section. The main insulation of the SJB is a polypropylene laminated paper (PPLP) which is the same as that of the DC HTS power cable. In order to separate the cooling section, an epoxy spacer is located at the center of the SJB. For the insulation design of the SJB, DC electric field analysis should be done to determine the shape of insulation structure and their physical dimensions. As DC field distribution was mainly determined by the ratio of electrical conductivity of the insulating materials, information about the electrical conductivity of dielectric material should be obtained. But the reliable data of electrical conductivity of insulating material, especially in cryogenic environment could not be easily obtained. In this paper, we focused on the measurement of electrical conductivity of PPLP in LN 2 according to the existence of copper deposition. Due to the infiltration of LN 2 between the edge of the electrode and PPLP, the accuracy of measured electrical conductivity might be lowered. Thus, in order to prevent the infiltration of LN 2 into PPLP specimen, PPLP specimen deposited by copper was adopted. On the basis of the measurement of PPLP in LN 2 , the initial SJB model was designed based on the joint box for a conventional AC oil-filled (OF) power cable. Then, two kinds of improved SJB models with different epoxy spacer configurations were considered and simulated using the finite element method (FEM). Consequently, it was possible to design the insulation structure of the SJB of a DC HTS power cable based on the DC electric field analysis.

This paper reports that development cases of charger with various charging functions. The developed charger has functions of temperature compensation charging mode, pulse charging mode, trickle charging control, reverse connecting protection and it can recycle the battery which is the performance degradation by converting charge and discharge mode. In addition, the proposed charger structure is designed as module method consisting of control, charge, and discharge parts so it is excellent in extension and can be set with various modes by control module. This paper describes the operating characteristics of these chargers and reports performance verification based on various experiment results.

Novel Deep Trench Buried-Body-Contac (DBBC) has been successfully developed for 4F2 DRAM cells on sub-30nm technology node. The critical requirements of thermal stability, shallow junction depth, and conformal source-drain doping profile for the contact are achieved by using an ultra thin Ti silicide ohmic layer and PLAD technique, which also show excellent electrical performance and process feasibility for the development of 4F2 DRAM cell on the 30nm node and beyond.

Dry-air is recognized as an attractive insulating medium for substituting SF 6 gas in high voltage devices. Recently, Japanese manufacture announced that 72.5 kV has been successfully developed using dry-air as a main insulating medium. However, only a few fundamental research works of dry-air have been reported compared to those of SF 6 . In this paper, two kinds of experiments were conducted to clarify the breakdown characteristics of dry-air. First, the effect of humidity on the breakdown characteristics of dry-air was deeply investigated. And secondly, the effect of electrode roughness on the breakdown voltage of dry-air has been investigated. In order to make artificial specific humidity of dry-air, the experiment chamber has been controlled in vacuum condition under 0.2 Torr and some water was injected before filling the dry-air. Dry-air used for the experiments was composed of about 21% Oxygen and 79% nitrogen and its humidity was controlled of ‒85°C dewpoint temperature. Water could be successfully vaporized in dry-air, and then AC withstand test and lightning impulse breakdown test were performed using sphere to plane electrode airgap configurations. Next, similar breakdown tests were performed considering polished condition, and artificially made surface roughness with 16 μm and 25 μm on the high voltage electrode respectively. From the test results, it was shown that impulse breakdown voltages were slightly decreased with increasing electrode roughness. However, AC withstand voltages did not show any remarkable difference regarding surface roughness, and it was revealed that the breakdown voltage of dry-air was not affected by different humidity condition ranging from 300 PPM to 1,500 PPM humidity in dry-air. AC withstand voltage and negative impulse voltage in this humidity range did not show noticeable difference.

A new method to reduce 120Hz output voltage ripple of LLC resonant converter using resonant controller is proposed in this paper. In the proposed control method, the resonant controller can give very high gain at this frequency, so it can reduce 120Hz output voltage ripple significantly. Employing the resonant controller in software, along with the conventional PI controller, the proposed technique can reduce 120Hz ripple without the additional circuit and cost. 2kW prototype experiment presents the results that verify the validity of the proposed method

Since the discovery of high-temperature superconductor (HTS), liquid nitrogen(LN 2 ) has not been only utilized as a coolant of superconducting electric equipment but also as an insulation material in cryogenic environment due to its dielectric performance. It also has a lot of advantages over other cryogenic liquid such as less expense and harmless substance, thus it has been widely used in the development of superconducting devices. Up to now, a lot of research works dealing with the breakdown characteristics of LN 2 for distribution-class superconducting devices have been presented worldwide but, few research works about breakdown characteristics of liquid nitrogen in extra high voltage class have been reported due to the limitation of cryogenic test facilities in extra high voltage (EHV) class. In order to study the cryogenic EHV insulation technologies, we have built the cryogenic dielectric test facilities including a fiber reinforced plastic (FRP) big cryostat with cryogenic bushing, a 400 kV AC overvoltage and a 1.6 MV lightning impulse test systems. Using these facilities, we focused on the breakdown characteristics of liquid nitrogen in EHV level which is rather different comparing to the distribution level. With real scale big cryostat, AC overvoltage test and impulse tests have been performed. From the test results, the breakdown characteristics of liquid nitrogen in EHV were suggested. And these test results could be used as basic insulation design data to develop transmission-class superconducting electric equipment.

This paper presents a new single carrier wave comparison PWM method for 3 level 3 phase Vienna type rectifier. The theoretical background for the single carrier wave comparison PWM is presented. The model for this Vienna rectifier is reviewed briefly and the voltage unbalance problem according to the offset duty is analyzed. Finally, the simulation and experimental results prove the effectiveness of the analysis results.

Conventional protection devices installed for the protection of excessive fault current in the electric power system have a certain response time delay resulting in power system to pass initial peaks of fault current. Superconducting Fault Current Limiter (SFCL) is a novel technology which has negligible power loss and capability to quench initial fault currents instantly and it also could be utilized to cope with excessive fault current problems in upcoming microgrids. This paper presents feasibility analysis results of positioning of the SFCL and its effects on reducing fault current in microgrids. The detailed power system having AC and low voltage DC microgrids consist of integrated wind and photovoltaic farms integrated with a traditional power system is modeled. Transient analyses for the microgrids were performed for the worst case faults with SFCL installed at key locations of the microgrids. It has been observed that SFCL should not be installed directly at the substation or the branch network feeders. This placement of SFCL results in abnormal fault current contribution from the DG sources. The strategic location of SFCL in power grid which limits all fault currents and has no negative effect on the DG sources is found to be in front of the point of integration of the DG sources with the microgrid.

New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.

This paper presents the analysis of voltage faults of the grid-connected inverter of a 3MW wind power generation system (WPGS). The analysis using a real time digital simulator (RTDS) is performed and evaluated for voltage faults to enable to withstand voltage dips during transient disturbance. For validation, typical voltage sag conditions and faults are deployed to the system. Simulation and experimental results validate that the analytical model is introduced and implemented under transient grid conditions.

The input voltage distortion in the three phase PWM rectifier is a main factor in the input current distortion and the voltage ripples across the DC link capacitor. This paper presents the MRAS(Model Reference Adaptive System) based input current harmonics reduction for the PWM rectifier under the input voltage distortion. The dq compensating voltages produced from the dq current difference between real system and the estimator model make up for the effect of the source voltage harmonics on the phase currents. The performance of the proposed algorithm is verified through the simulation and the experiment.

This paper presents voltage transient analysis of a proposed 3MW permanent magnet synchronous generator (PMSG) wind power generation system (WPGS) using a real time digital simulator (RTDS). The WPGS that is modeled with realtime digital simulator (RTDS) and RSCAD simulators are characterized for voltage transient analysis. Furthermore, a newly actual controller-hardware-in-the-loop simulation (CHILS) is employed to analyze voltage transient to the system. For validation, two typical voltage sag conditions are considered as three-phase-line to-ground and single-line-to-ground faults. Experimental results validate that the modeled system operates safely under transient grid conditions by pitch control as well as circuit breaker operation.

This paper describes the design and performance of a 10-Gb/s optical receiver front-end fabricated in a 0.13-μm CMOS technology. To realize a wide bandwidth transimpedance amplifier (TIA) that has large input parasitic capacitance, an area-efficient stacked spiral transformer is implemented. By using a capacitance multiplication technique, the baseline wander resulting from a current offset cancellation is minimized. The TIA achieves a transimpedance gain of 58.5dB£i, an area of 0.02mm2, and a bandwidth of 7.9GHz. The limiting amplifiers (LAs) following the TIA use negative impedance converters to enhance the bandwidth. The TIA and the LAs consume 5mW and 28.4mW, respectively with a supply voltage of 1.2V.

Gradient-Index Plastic Optical Fiber (GI-POF) offers significant potential as an ultra-high bandwidth communication medium for EMI-free all-optical network architecture that is especially suitable for gigabit Internet home networking service. Recent advances in GI-POF are discussed.

Effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related effects, device characteristics under mechanical bending stress and stressor layers were compared. The compressive stressor device exhibits improved initial interface quality, although slightly degraded reliability characteristics, due to increased hydrogen passivation of the dielectric/substrate interface. Thereby, the hydrogen passivation in the interface is found to be a primary cause of the difference in reliability characteristics.

A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.

In comparison with conventional electromagnetic motors, ultrasonic motors have many advantages such as a large torque at the low velocity, good controllability, rapid response, quiet operation, simple structure and non electromagnetic field induction, etc. These features have led to the development of various ultrasonic motors in many industrial fields. Hence, in this study, ultrasonic linear motor using multilayer structured ceramic actuator was designed and simulated using ANSYS of finite element method(FEM) simulator for investigating the optimum conditions of it. The ultrasonic linear motor studied in this paper was designed using the 1st longitudinal (L1) and 4th bending (B4) vibration. The size of ceramic actuator is 15 mm long and 5 mm wide. And one-layer thickness of actuator is 60 mu m. The dimension of linear motor is 61 times 5 times 3 mm. The sectional size of projection is 1.5 times 5 mm. The driving voltage of the motor was very low as 5 Vrms. With the increase of the number of piezoelectric ceramic layers, displacement of node was increased up to 21 layered ceramic actuator and then decreased. Maximum z displacement of node was about 7.02 mum at the 21 layered ultrasonic motor.

An unmanned surveillance robot consists of a machine gun, a laser receiver, a thermal imager, a color CCD camera, and a laser illuminator. It has two axis control systems for elevation and azimuth. A human guard can be replaced with such a robot system to take care of dangerous surveillance tasks. However, the robot system is mounded at a fixed post to take care of surveillance tasks. In order to watch blind areas, it is necessary to modify such a surveillance robot to be installed on an UGV (Unmanned Ground Vehicle) system. Thus, it is required to have a stabilization system to compensate the disturbance from the UGV. In this paper, a simulation based design scheme has been adopted to develop a mobile surveillance robot. The 3D CAD geometry model has first been produced by using Pro-Engineer. The required pan and tilt motor capacities have been analyzed using ADAMS inverse dynamics analysis. A target tracking and stabilization control algorithm of the mobile surveillance robot has been developed in order to compensate the motion of the vehicle which experiences the rough terrain. A virtual motion simulator which reproduces UGV motion has also been developed for a virtual testing of the mobile surveillance robot. To test the performance of the stabilization control system of the robot, ADAMS/simulink co-simulations has been carried out.

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.

This paper describes a quad 3.125 Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase-averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1 UI. Implemented in 0.13 CMOS, the transceiver tolerates up to 0.67 UI of total jitter at 3.125Gbps.

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

In this paper, a novel, wearable cardiac monitor (hereafter called WHAM) is proposed which allows a continuous and real-time monitoring of user's cardiac conditions. The proposed device is composed of 3 main components: a disposable electrode, a controller, and personal gateway (e.g., cellular phone, PDA, and smart phone etc.). The ECG signal is recorded according to the surface Laplacian of the body surface potential. We investigated the feasibility of WHAM as a wearable ambulatory device for continuously and on-line monitoring a user's cardiac conditions. To this end, the ECG signals recorded with WHAM were compared with those obtained by Wilson's unipolar chest leads, that is, v1 to v6. As a result, the ECG signals recorded with WHAM showed the similar morphology to Wilson's unipolar chest leads (v1 to v6) with the exception of P and T waves, although there is a difference between amplitudes of both signals. Also, it is shown that the R-peaks are accurately detected by the algorithm at the accuracy of more than 99% for the ECG signals of WHAM recorded during resting and walking. From these results, it is found that the WHAM shows enough feasibility and has advantages as a wearable ambulatory monitoring device in that the hardware is miniaturized enough small to integrate on a small region, thereby no wire leads need.

A 10 Gb Ethernet transceiver chip integrated with 10 Gb/s serial and quad 3.125 Gb/s XAUI interfaces is implemented in 0.13 /spl mu/m CMOS and dissipates 898 mW from 1.2 V. A digital coarse control algorithm for VCOs reduced the VCO gains for noise immunity. A blind oversampling technique enabled synthesis of the XAUI interface.

In this paper, we present the development work of anisotropic conductive adhesives (ACA) with particular emphasis on the enhanced thermal conductivity of ACAs for flip chip applications. To ensure good thermal conductivity, we incorporated silicon carbide (SiC) fillers in the ACA formulation. For the characterization of modified ACAs with enhanced thermal conductivity by loading different content of SiC fillers, measurements of thermal conductivity and thermomechanical analyses such as dynamic scanning calorimetry (DSC), dynamic mechanical analysis (DMA), and thermomechanical analysis (TMA) were performed. The current carrying capability and reliability of flip chip joints using conventional ACA and novel ACA with enhanced thermal conductivity were compared to investigate the role of ACA as a new thermal transfer medium in the flip chip assembly. We developed a new ACA with high thermal conductivity which can improve reliability under high current stressing. This paper is part of a broad study of thermally conductive ACAs for flip chip packaging and other electronic packaging technologies.

PRAM is a promising memory that can solve the problems of conventional memory. Writing current reduction is the most important technical challenges in order to maximize the advantage of PRAM in scaling. We will present the high density 64Mb PRAM based on 0.18 /spl mu/m CMOS technologies. And Various approaches to reduce the writing Current will be reviewed.

PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18/spl mu/m CMOS technology.

Detection wavelength tuning of quantum well infrared photodetector (QWIP) has been carried out by using impurity free vacancy disordering (IFVD) technique with SiO/sub 2/ capping layer. The detection wavelength of QWIP was changed from 8.2/spl mu/m to 10/spl mu/m due to bandgap change by intermixing of constituent atoms in multiple quantum well (MQW) absorption region in Fig.1. The red-shift in detection wavelength can be explained by gap narrowing between confined state and continuum state in conduction band, which is a consequence of blue-shift in MQW bandgap after intermixing in Fig.2. The bandgap of the intermixed MQW structure was theoretically investigated. The Al-Ga inter-diffusion, which induces the red-shift of detection wavelength from 8.2/spl mu/m to 10/spl mu/m, was calculated to be 7/spl Aring/ at 850/spl deg/C.

Anisotropic conductive adhesives have been considered and evaluated as promising interconnect materials for flip chip assembly in the applications for low cost, high-density and high speed interconnection packages. In this paper, we have evaluated and compared several flip chip interconnects using anisotropic conductive adhesives at RF and high frequency range. The performances of highspeed circuits are limited by package interconnect discontinuity doe to large inductance and resistance in the high frequency range. This discontinuity is determined by the interconnection geomehy and materials used. For bumps on the IC, Au stud, Au electroplated and electroless Ni/Au were used, and for the interconnection adhesives, two kinds of ACFs with different dielectric constant were used. The high kequency measnrements were performed on the test flip chip vehicles using different bonding materials to evaluate high frequency model parameters based upon ACF flip chip model and network analysis. We applied these ACFs flip chip technologies to the assemblies of passive device using RF IPD (Integrated Passive Device) and active device using RF active MMIC device on RF module to demonstrate real applications of ACF interconnection at RF and high frequency range, and compared the results with those of flip chip assembles using conventional methods such as solder ball interconnection. The reliability of ACF flip chip interconnects was also investigated by various environmental tests, such as thermal cycling test (-55 OC/+125 "C, 1000 cycle), high temperature humidity test (85 'C/85%RH, 1000 hours) and high temperature storage test (150 OC, dry condition) to evaluate the effect of environmental attacks on the electrical stability of ACF flip chip assemblies.

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18/spl mu/m-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns.

Summary form only given, as follows. Summary form only given. Detection wavelength tuning of a quantum well infrared photodetector (QWIP) has been carried out by using the dielectric cap quantum well intermixing technique with plasma enhanced chemical vapor deposited SiO/sub 2/ capping layer.

Summary form only given, as follows. Summary form only given. Intermixing effects of MBE (Molecular Beam Epitaxy) grown InGaAs SAQDs (Self-Assembled Quantum Dots) covered with SiO/sub 2/ dielectric capping layers, which was grown by PECVD, were investigated. After the thermal annealing, photoluminescence (PL) measurement has been carried for the optical characterization at the room temperature quantum well with PECVD-grown SiO/sub 2/ capping layer.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.

A new DRAM cell scheme using merged process with storage node and memory cell contact called BC is introduced for free alignment tolerance between memory cell contact and storage node. The new cell scheme and conventional COB stacked cell scheme are compared for the misalignment tolerance and photo and etch process issues. The new cell scheme is processed in 0.15 /spl mu/m minimum feature size and its results are described including vertical SEM pictures, capacitance-voltage data, and leakage current. This new cell scheme achieved the requirement of memory cell capacitance of 25 fF/cell in 0.30 /spl mu/m pitched 4 Gb DRAMs.

A reliable 1T/1C ferroelectric RAM has been successfully fabricated with 1.2 /spl mu/m conventional CMOS technology by adopting IrO/sub 2/ electrode and the Ti-rich PZT thin film. The Ti-rich PZT capacitor shows no degradation of sensing Pr after integration process. After 1/spl times/10/sup 10/ cycling, the loss of remnant polarization was less than 5%. In thermally accelerated (150/spl deg/C) test condition, more than 14 /spl mu/C/cm/sup 2/ for both data 0 and data 1 sensing Pr values are obtained even after 10 years.

Non-conductive adhesives (NCA) are one of the interconnection materials widely used in display packaging and flip chip packaging technology, especially for fine-pitch interconnection. NCA interconnection in flip chip assembly has many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. We have developed new NCA materials, film type, for flip chip assembly on organic substrate such as FR-4 printed circuit boards (PCBs). NCAs are generally mixture of epoxy polymer resin without any fillers. As a result, NCAs have higher CTE values than conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on FR-4 boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was lowered by filling of nonconductive fillers of diameter below 1 gm. The modified NCA in flip chip interconnection between gold stud bumps of a chip and metal pads of PCB substrates show highly reliable interconnection when exposed to various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 hours) and high temperature storage test (125/spl deg/C, dry condition).