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This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper. [ABSTRACT FROM AUTHOR]

Integration of discrete radios onto a single-silicon CMOS substrate [1]-[6], followed by commercialization of single-chip cellular, Bluetooth, and Wi-Fi radios [7]-[9], has shaped the wireless world that we live in today. Although integration of wireless transceivers with powerful microprocessors in very large systems on chip (SoCs) is currently commonplace in consumer electronics, the demand for lower power consumption, higher effective data rates, and higher network capacity continues to drive research on integrated radios. By some estimates, the demand for mobile data per volume area will increase 1,000x during the next decade, with end-user data rates increasing by as much as 10-100x [10]. [ABSTRACT FROM AUTHOR]

A fully integrated transformer-based tunable impedance-matching network is described. The tuning network independently tunes the real and imaginary parts of the impedance. A test chip implemented in a 40-nm CMOS process achieves the resistive tuning range of one octave, making it suitable for shared Bluetooth/Wi-Fi power amplifier (PA) applications. The main sources of insertion loss are identified, and strategies to minimize the insertion loss while maximizing the tuning range of the real and imaginary parts are discussed in this brief. [ABSTRACT FROM PUBLISHER]

A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash comparators are strobed immediately after the coarse phase to achieve a high sampling rate. The systematic offset voltage between the coarse and fine phase manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. In this work, the offset is cancelled with background calibration by residue range correction circuits in the following stage's sub-ADC. In addition, the sub-ADC's random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. The reference buffer, bias circuitry, and digital error correction circuits are all integrated on a single chip. The ADC occupies an area of 0.282 mm^2 in 55 nm CMOS technology and dissipates 30.7 mW. It achieves 64.6 dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s. [ABSTRACT FROM PUBLISHER]

This paper proposes a multistage transformer-feedback-based design approach for a high fractional-bandwidth (fBW) IF stage in a 60-GHz heterodyne receiver. An in-depth analysis of source-to-gate transformer-feedback amplifiers, including the design of the matching network, is presented. Analytic expressions for the input resistance, quality factor, and noise figure (NF) as a function of the transformer turns-ratio (n) and magnetic coupling factor (k) are derived. To validate the proposed analysis, a wideband IF amplifier and mixer were designed in a 40-nm CMOS process. From measured results, this device achieves a 16% -3-dB fBW, a peak power gain of 27.6 dB, an NF of 5.3 dB while consuming 28.8 mW from a 0.9-V supply. [ABSTRACT FROM AUTHOR]

A reconfigurable bandpass continuous-time \Sigma \Delta RF ADC tunable over the 0.8–2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 \mum CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is -74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz. [ABSTRACT FROM PUBLISHER]

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-µm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm². [ABSTRACT FROM AUTHOR]

The article discusses various reports published within the issue including one by P. Haldi and colleagues on linear power amplifier, K. H. An on power-combining transformer techniques, and B. A. Floyd on frequency synthesizer capable of generating 55.8 to 65.8 GHz.

The article discusses various reports published within the issue, including one by B.K. Ahuja, H. Vu, C.A. Laber and W.H. Owen about the application of the floating gate device as a voltage reference.

A correction to the article "Analysis and Design of a Transformer-Feedback-Based Wideband Receiver" that was published in the June 18, 2013 issue is presented.

This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper.

A current-mode interface chip for Silicon Photomultiplier (SiPM) array based positron emission tomography (PET) imaging front-ends is described. The circuit uses a high-speed current amplifier with a low input impedance, to minimize signal loss at the SiPM amplifier interface. To reduce the impact of dark noise, a novel high-speed threshold detection/comparator circuit is used to remove unwanted noise events. A prototype chip interfaces an array of SiPMs to the digital backend of a Positron Emission Tomography (PET) system using 64 readout channels, each of which contain a current amplifier and a threshold detection component. To reduce the number of backend channels, a row-column pulse positioning architecture (RCA) has been implemented. The ASIC occupies an area of 14.04 mm 2 in 130nm STMicroelectronics HCMOS9GP process. The measured input impedance of the current amplifier is 20 ohms at 10 MHz, while the threshold detection circuit's propagation delay is 0.3-2ns.