1. Comprehensive Reliability Study of STT-MRAM Devices and Chips for Last Level Cache Applications (LLC) at 0x Nodes
- Author
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Yuan-Jen Lee, Yang Yi, Renren He, Vignesh Sundar, Huanlong Liu, Vinh Lam, Son Thai Le, Jodi Iwata-Harms, Sahil Patel, Shen Dongna, Jesmin Haq, Luc Thomas, Ru-Ying Tong, Santiago Serrano-Guisan, Hideaki Fukuzawa, Tom Zhong, Po-Kang Wang, Guenole Jan, Jeffrey Teng, Yu-Jen Wang, and Jian Zhu
- Subjects
Tunnel magnetoresistance ,Magnetoresistive random-access memory ,Reliability (semiconductor) ,Computer science ,Reliability study ,Cache ,Static random-access memory ,Write margin ,Soft breakdown ,Reliability engineering - Abstract
To consider STT-MRAM as an SRAM replacement, the reliability of the MTJ devices has to be demonstrated. A comprehensive study of degradation of STT-MRAM magnetic tunnel junction barrier under stress is presented in this paper. It is found that the breakdown mechanism of such devices follows a consistent path of soft breakdown (SBD) followed by hard breakdown (HBD). We discuss the strategy to improve the write margin by reducing the resistance area product (RA) of the tunnel barrier. Finally, we link our single device reliability studies to similar endurance studies performed on our fully functional chips.
- Published
- 2019
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