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In this paper, we examine the feasibility of FPGA as a platform for training a convolutional binary-weight neural network. Training a neural network requires more data movement compared to inference. Acceleration of training on an FPGA is, therefore, a challenge because the data movement increases off-chip memory accesses. We try to address this problem by storing most of the data in the on-chip memory and adopting batch renormalization. This allows for training a large network by reducing the required intermediate data and its movement. For the case where all data except the input images can be stored on an FPGA chip, we present an accelerator for training CNNs to classify the CIFAR-10 dataset. Further, we study the impact of network size on performance and energy of FPGA and GPU. Our accelerator mapped in the Arria 10 FPGA chip obtains up-to 9.33X higher energy efficiency compared to the Nvidia Geforce GTX 1080 Ti GPU at similar performance.

Estimating the current memory capacity of a neural network based recognition system is critical to maximally use the available memory capacity in memorizing new inputs without exceeding the limit of the capacity (catastrophic forgetting). In this paper, we propose a dynamic approach to monitoring a network's memory capacity. Prior works in this area have presented static expressions dependent on neuron count N, forcing to assume the worst-case input characteristics for bias and correlation when setting the capacity of the network. Instead, our technique operates simultaneously with the learning of a Hopfield network and concludes with a capacity estimate based on the patterns which were stored. By continuously updating the crosstalk associated with the stored patterns, our model guards the network against overwriting its memory traces and exceeding its capacity. We designed a fingerprint recognition system based on our dynamic estimation technique. With the experiment using NIST Special Database 10, the system achieves 2.7 to 8X larger memory-capacity as compared to the baseline systems using the static capacity estimates.

We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.

Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.

This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.