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The boundary-scan test technology can be used for the test of complex circuits. Before the test, the integrity of the boundary-scan structure needs to be tested. Through the study of the boundary scan structure, this paper designs the upper computer software, tests the boundary-scan structure, and successfully checks the condition of the boundary scan link.

Recent advancements in VLSI technology have made possible to design entire systems onto a single chip, i.e. system-on-chip (SOC). It is necessary to carry out the tests of SOC in order to insure the correctness of the manufacturing process. Test scheduling is an important aspect for the tests of SOC, which determines an assignment of cores to test access mechanism such that the overall test application time is minimized. In this paper, a new test scheduling approach using evolutionary programming technique is presented, which uses the individuals to represent the feasible solutions of test scheduling problem, and makes many individuals to form the populations. The better scheduling schemes are obtained by the evolutions of the populations. The partitions for the total bandwidth of test bus, as well as the assignments of cores to test access mechanism, can be obtained simultaneously in the approach. Experimental results for the SOC benchmark circuits demonstrate the proposed approach can solve the test scheduling problem in reasonable time.

A new approach for detecting multiple faults in digital circuits is presented in this paper, which uses neural network technique to generate the test vectors and to diagnose the multiple faults. First of all, the optimal neural network model corresponding to an arbitrary digital circuit is used. For a logic circuit with m inputs and n outputs, the optimal neural networks having m+n neurons can represent the logic function of the circuit. Secondly, the test vectors of multiple faults in the circuit are obtained by using evolutionary strategies to compute the minimum energy states of the optimal neural network. Thirdly, the multi-layer feed forward network and back propagation algorithm are used to diagnose the multiple faults in the circuit. The design of both network configurations and samples patterns are given in detail. Experimental results show that the approaches proposed in this paper are effective for detecting and diagnosing multiple faults in digital circuits.

A new approach to generate test sets for multiple faults of digital circuits is presented in the paper, which employs neural networks and simulated annealing technique. The neural network models for circuit are built, the test vectors of multiple faults in the circuit can be produced by computing the minimum energy states of the neural networks. An algorithm based on simulated annealing is proposed to compute the minimum states of energy functions, the algorithm has global convergence and has polynomial complexity under a decrement scheme of temperature. Experimental results shows that it is possible to obtain high fault coverage for testable multiple faults with the proposed approach without fault simulation.

The testable realization techniques of logic functions can be used for circuit design to reduce the complexity of test pattern generation. The circuit testable realizations of multiple-valued logic functions are investigated in this paper. The multiplication modulo gates and addition modulo gates are used in the testable realization. It is shown that n+2 test vectors are sufficient to detect the Min and Max bridging faults in the testable realizations, where n is the number of input variables of multiple-valued functions. The delay in circuit can be decreased if the tree structure is employed instead of cascade structure. It is indicated that for the tree structure realizations with m-valued logic, the number of single fault test vectors is three if m-2 extra inputs and an addition modulo gate are added. Furthermore, the multiple faults detection approach of the circuit realizations is investigated, a multiple faults test set is given.

The multilevel test allows the complete testing for a circuit from the upper functional levels to the actual defective components. An approach for fault diagnosis of digital systems at hierarchical levels is presented, which employs bus observation technique and fuzzy neural networks to solve the acquirements of test information. It is shown that fault diagnosis can be done at any desired level by means of the analysis for fault information relativity and the testability of faults. The approach has been applied in a fault diagnosis system for a microcomputer; the experimental results show the effectiveness of the approach.