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With the development of automated vehicles and advanced driver assistance systems, the compression of the large amount of data generated by the vehicle camera sensors becomes a necessary processing step to improve the automated driving system efficiency. H.264 is a widely adopted video compression scheme, and it has been designed for human vision. Rate control in H.264 uses fixed quantisation parameter, however, this process can lead to fluctuation in different regions of the image quality of each frame. In this paper, we propose a two-stageH.264 based video compression framework, named “Two Stage Compression (TSC)”, to compress the automotive camera videos with different values of compression rate in different regions of each frame. In the first stage, each frame will be divided into the region-of-interest and the region-out-of-interest. In the second- stage, different compression ratios will be applied based on the importance of the region. The experimental results show that under the same overall compression ratio, our proposed TSC increments the semantic-aware PSNR by 3.213 dB compared to uniform H.264 compression. Our method is also compared to uniform H.264 compression using a segmentation algorithm, with an improvement of 1.77% in mIOU, the average Intersection over- Union

Thyristor-controlled LC-coupling hybrid active power filter (TCLC-HAPF) is characterized with low DC-link voltage and wide operational range, which was recently developed for power quality conditioning in the medium-voltage-level system. This paper proposes a fuzzy logic based adaptive source current total harmonic distortion (THD) controller for the TCLC-HAPF. The proposed controller can adaptively change the hysteresis band (HB) according to the reference THD value, thereby possibly reduce the switching loss and keep the source current THD at an acceptable reference level. Simulation is conducted for verifying the proposed controller, in comparison with the fixed HB controller.

This paper aims to review the state of the art of Light Detection and Ranging (LiDAR) sensors for automotive applications, and particularly for automated vehicles, focusing on recent advances in the field of integrated LiDAR, and one of its key components: the Optical Phased Array (OPA). LiDAR is still a sensor that divides the automotive community, with several automotive companies investing in it, and some companies stating that LiDAR is a ‘useless appendix’. However, currently there is not a single sensor technology able to robustly and completely support automated navigation. Therefore, LiDAR, with its capability to map in 3 dimensions (3D) the vehicle surroundings, is a strong candidate to support Automated Vehicles (AVs). This manuscript highlights current AV sensor challenges, and it analyses the strengths and weaknesses of the perception sensor currently deployed. Then, the manuscript discusses the main LiDAR technologies emerging in automotive, and focuses on integrated LiDAR, challenges associated with light beam steering on a chip, the use of Optical Phased Arrays, finally discussing current factors hindering the affirmation of silicon photonics OPAs and their future research directions.

Automated vehicles (AVs) are one of the breakthroughs of this century. The main argument to support their development is increased safety and reduction of human and economic losses; however, to demonstrate that AVs are safer than human drivers billions of miles of testing are required. Thus, realistic simulation and virtual testing of AV systems and sensors are crucial to accelerate the technological readiness. In particular, perception sensor measurements are affected by uncertainties due to noise factors; these uncertainties need to be included in simulations. This letter presents a framework to exhaustively analyze and simulate the effect of the combination of noise factors on sensor data. We applied the framework to analyze one sensor, the light detection and ranging (LiDAR), but it can be easily adapted to study other sensors. Results demonstrate that single noise factor analysis gives an incomplete knowledge of measurement degradation and perception is dramatically hindered when more noises are combined. The proposed framework is a powerful tool to predict the degradation of AV sensor performance.\ud

In this paper, we contribute an age estimation method towards dealing with low quality face images. This is a practical and important problem because an image we received may have low resolution or be affected by some noise via transmission. Upon reviewing the literature on facial age estimation, we notice that few articles tackle this low quality image based facial age estimation problem. In our framework, we propose a newly designed deep convolutional neural networks architecture, consisting of five major steps. Firstly, a data augmentation step is utilized to ease the training procedure. Secondly, we propose to use a super-resolution method to enhance the input images. Thirdly, we use a deep network to conduct gender grouping. Fourthly, two recently proposed deep networks are modified with depthwise separable convolutions to perform age estimation within male and female groups. Finally, a fusion procedure is added to further boost age estimation accuracy. In the experiment, we use two benchmark datasets, IMDB-WIKI and MORPH-II, to verify our proposed method and also show a significantly performance improvement over some state-of-the-art methods.

In this paper, a deep Convolutional Neural Network CNN based system, called Depthwise Separable Convolutional Neural Network (DSCNN) fusion system, for human facial age estimation is presented. This system includes following four stages. In the first stage, a data augmentation procedure is utilized to enrich the dataset. In the second stage, a pre-trained deep CNN model is fine-tuned for the gender classification task. For the third stage, three newly designed DSCNN age estimators are utilized to conduct gender-specific age estimation for gender grouped facial images from previous stage. The architectures of these three deep DSCNNs are constructed to lower computation complexity. In the last stage, estimated ages from three DSCNN age estimators are fed to the fuser to boost the overall age estimation performance. In the experimental results, on four benchmark datasets, IMDB-WIKI, MORPH-II, and ChaLearn LAP Apparent age V1 and V2, the proposed system demonstrates a significant performance improvement over the state-of-the-art deep CNN models and methods.

Column driver is an important component for LCD application. In this work, a new Complementary Cross-Coupling Operational Transconductance Amplifier (CBCC-OTA) featured with simple architecture is presented. Using 65nm CMOS technology and a 1.2V supply with 12.7 μ A supply current at typical case, the simulation results of the proposed OTA with slew rate enhancement (SRE) has achieved a DC gain of 66.2 dB, settling time of 1.6 μ s, average slew rate of $1.225\mathrm {V}/ \mu \mathrm {s}$, gain bandwidth (GBW) of 917 kHz, and signal-to-noise ratio (SNR) of 79.1 dB for 150 pF load. The performance comparison has validated that the key performance metrics of the proposed OTA outperforms the representative works.

In this paper, we proposed a stacked deep network fusion model for the apparent human facial age estimation. Three well-performed deep architectures are utilized in the first three stages and the estimation results for each architecture are fused in the last stage to boost the overall performance. In the first stage, a pre-trained deep CNN model is fine-tuned for the gender classification task. For the second stage, two gender-specific age groupers are built to classify the facial images into two nonoverlapping age groups. In the third stage, ages are estimated from the three deep networks and fed to the fuser of the last stage to refine age estimation results. Experimental results demonstrate a significant performance improvement of the proposed approach over the state-of-the-art deep CNN models.

A novel relaxation oscillator (ROSC) with a merged window comparator, an optimized parallel/series composite resistor and a reference generator on the basis of threshold monitoring circuit is presented. The ROSC achieves offset cancellation by adopting the merged window comparator. The optimized composite resistor is employed to reduce the output frequency temperature coefficient (T.C.) even in the presence of process variation. The oscillator is realized in 65nm CMOS process. At a supply voltage of 1.2V, the current consumption is 7.47μΑ. The simulated frequency T.C. is 14.69ppm/°C over the temperature range of −20∼120°C and the line sensitivity is 0.188%/V over the supply voltage range of 1.2∼2.3V.

This paper presents a current feedback buffer based output capacitorless low-dropout (OCL-LDO) regulator. By incorporating the weighted current feedback (WCF) circuit technique in a simplified buffer-based regulator architectural design, it can provide a fast response with efficient transient figure-of-merit (FOM) for wide current (I L ) and capacitive (C L ) load range. Validated in a UMC 65-nm CMOS process technology, the measurement results have confirmed that this regulator can deliver a maximum I L of 100 mA with overshoot/undershoot not more than 72 mV for a C L range from 470 pF to 10 nF under a 0.9V supply whilst consuming a quiescent current (I Q ) of 14.4 µA. From the performance comparison results, the proposed circuit has achieved excellent transient FOM and displayed small overshoot/undershoot. More importantly, it offers sustainable transient parameters and transient FOM for wide C L and I L range.

This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 μA. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.

Circulation is a very essential parameter to assess the intensity of a wake vortex, and there is a great demand of real time retrieval of wake vortex circulation in aviation safety and related area. In this paper, by taking into account the weak inertia of aerosols inside the wake, we present a new algorithm to retrieval the circulation of wake vortex in clear air with an up/down-ward scanning Lidar, where the circulation is boiled down to the solution of a simple system of linear equations. Application of the algorithm on measurement data from Hong Kong International Airport (HKIA) verifies the good performance of the algorithm.

This paper presents a new low-frequency filter dedicated to the linear sensor applications. The CMOS active capacitor is bootstrapped by the embodiment of an operational amplifier (op-amp) based active capacitor into another op-amp based capacitor multiplier through using shared amplifier architecture for obtaining simplification. The proposed active capacitor forms a monolithic R-active-C low-pass filter (LPF) with a passive resistor. The simulation results, on the basis of AMS 0.35 μm CMOS models, have shown that a 2nd order 200Hz LPF can achieve a Total Harmonic Distortion (THD) less than −53 dB at 2 V pp and 40 Hz in a single 3.0 V supply, with a current consumption of 106 μA. Compared with the MOSFET-C and Gm-C counterparts, it significantly displays better linearity whilst offering high signal(Vpeak)/V DD ratio in terms of efficiency in supply utilization.

This paper presents a 1MHz ring oscillator with simple temperature compensation circuit dedicated to MEMS sensor applications. A closed-loop PTAT voltage source follower coupled with an open-loop replica-biased source follower driving structure is proposed to power the CMOS ring oscillator and counteract its temperature-dependent effect. In conjunction with a pseudo-resistor based low-pass filter to lower the circuit noise, it significantly improves the jitter performance. The circuit is realized using 0.35μm CMOS technology at a 5V supply. The frequency variation of the compensated oscillator over the temperature range of-- 40°C to +90°C is-- 0.1% to +0.19% (22.3ppm/°C) with respect to the uncompensated frequency variation of-- 12.1% to +21.6% (2592ppm/°C) at typical process. For worst case process, the frequency deviates from-- 1.5% to +1.9% for the stated temperature span and it deviates from-- 1.2% to +1.2% at ±10% supply variation under 1 MHz oscillation frequency. The proposed ring oscillator is insensitive to the PVT variations. The simulated cycle-to-cycle RMS jitter value due to both the intrinsic circuit noise and the 200mV peak-to-peak power supply noise is only 64ps, which is about 50 times smaller than that of the standard ring oscillators under identical process technology and design conditions.

An ultra-low power, low-noise, high power supply rejection (PSR) op-ampless regulator is presented in this paper. It uses a native composite power transistor plus a sandwich on-chip native capacitor in the pre-regulator to enhance broadband high PSR performance. Besides, a pseudo-resistor based low-pass filter is used to reduce the Brokaw's voltage regulator circuit noise. Realized using GlobalFoundries 1.8V/3.3V CMOS 0.18µm process, the regulator gives a mean output 0.992V for 8 samples while occupying a silicon area of 0.095mm2. It consumes only 1.28µA and drives a maximum output current of 2mA. The measured output noise is 80.1nV/vHz at 1kHz and 14.2nV/vHz at 100kHz while the integrated output noise over 10Hz–100kHz bandwidth is 13.88µVrms. The measured PSR is −79.1dB @ 10Hz, −55.3dB @ 1MHz and −41.6dB @ 10MHz. The proposed regulator is useful for sensor circuit applications using energy harvesting power source.

This paper presents an improved design for the low-dropout regulator (LDO) based on the Flipped Voltage Follower (FVF) structure. A FVF based LDO regulator with composite power transistor (CPT) is proposed. It reduces the minimum biasing current requirement of the power transistor in Single-Transistor-Control (STC) LDO regulator whilst enhancing the loop gain as well as bandwidth performance. The proposed LDO regulator has been validated using GLOBALFOUNDRIES 0.18-μm CMOS process. Using the FVF STC structure as the benchmark, the simulation results have shown that the proposed CPT LDO regulator has a better load transient and accuracy than that of the STC and Buffered Flipped Voltage Follower (BFVF) counterpart whilst maintaining low voltage operation.

A new ultra-low voltage and power digital comparator using analog offset calibration technique is presented in this paper. The comparator's input transistors are working in subthreshold region for the entire input range and is used as a zero crossing detector for the analog offset calibration technique. Realized using GLOBALFOUNDRIES 0.18μm CMOS process technology, at the voltage supply of 0.7V and 1MHz clock frequency, the standalone comparator dissipates 153nW but increasing to 494nW with calibration function. For voltage supply down to 0.4V and 20 kHz clock, the single comparator dissipates only 8.054nW. The calibration circuit is capable of reducing a 20mV of input-referred dc offset down to 655.3μV, making it suitable for 10-bit biomedical SAR ADC applications.

An improved dynamic-biased CMOS operational amplifier for biomedical circuits is presented in this paper. The proposed ultra-low power operational amplifier comprises a weak-inversion biased differential input stage, a pseudo class-AB output stage and a multi-phase master bias dynamic biasing circuit. Using GLOBALFOUNDRIES 0.18 μm CMOS process, the proposed amplifier, without dyamic biasing circuit, consumes a static supply current of 5.94 μA at a 1.8V supply. The simulated result shows a DC gain of 89.63dB and an unity gain bandwidth of 2.55 MHz at a capacitive load of 30.5 pF. When activating the proposed dynamic biasing circuit to the same amplifier in a reported sample-and-hold (S/H) circuit for biomedical application, the S/H circuit consumes 8.16 μW at a sampling frequency of 128 kHz. In response to 1-Vpp and 1-kHz sinusoidal input, the S/H circuit has achieved −76.67 dB of total harmonic distortion (equivalent to 12.73 bits of linearity-based ENOB) and 5.21×10–3 μA/MHz of Figure of Merit.

This paper presents a new low-voltage output capacitorless low dropout (LDO) voltage regulator for System-on-Chip (SoC) applications. A low-impedance loading network is introduced at the output of LDO to achieve full range stability from 0 to 100 mA load current at a 100 pF parasitic capacitance load. No minimum output load current is needed whereas the quiescent current is made low. Thus, it improves the efficiency for light load currents. The proposed LDO has been validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO consumes only 14 µA at 0 load current, regulating the output at 1 V from a minimum 1.2 V supply, with a dropout of 200 mV at the maximum load current of 100 mA. The worst case full-load transient response is about 3.96 µs.

This paper presents a new 1.2V high power supply rejection (PSR) voltage reference. The proposed design employs a high-PSR pseudo floating voltage source and a differential-to-single-ended R.MOS Capacitor signal-conditioning circuit to achieve high PSR performance metric. The high-PSR pseudo floating voltage source consists of the merged design of two Brokaw's reference circuits. The proposed bandgap voltage reference is designed and simulated using CSM 1.8V/3.3V 0.18µm CMOS process technology. At a single 3.3V supply, the simulation results have shown that the reference output voltage can achieve a temperature coefficient of 24.5 ppm/°C over the temperature range from −40°C to 125°C. The PSR is −92.2 dB at dc or very low frequency, −61.8 dB at 1MHz and −42.7 dB at 10MHz, thereby showing that the proposed voltage reference is suitable for DC-to-DC converter applications.

Conventional Weaver receivers select the signal channel and reject the image. This paper offers a simple method making it possible to select either signal or image by a single LO frequency. As a result, the number of LO frequency locations can be reduced by half, thereby relaxing the RF integer-N PLL frequency synthesizer requirements.

Current research based on various approaches including the use of numerical prediction models, statistical models and machine learning models have provided some encouraging results in the area of long-term weather forecasting. But at the level of meso-scale and even micro-scale severe weather phenomena (involving very short-term chaotic perturbations) such as turbulence and wind shear phenomena, these approaches have not been so successful. This paper focuses on the use of chaotic oscillatory-based neural networks for the study of a meso-scale weather phenomenon, namely, wind shear, a challenging and complex meteorological phenomena which has a vital impact on aviation safety. Using LIDAR data collected at the Hong Kong International Airport via the Hong Kong Observatory, we are able to forecast the Doppler velocities with reasonable accuracy and validate our prediction model. Preliminary results are promising and provide room for further research into its potential for application in aviation forecasting.

A card-centric framework is proposed to expand smart cards' potential and perhaps help smart cards to survive in the ever-changing world of consumer electronics. In the card-centric framework, smart cards play an active role and control their own I/O devices. The card-centric computer is an implementation of the card-centric framework and can work as a fully functional computer. It demonstrates the ability of smart cards to have control over the mouse, keyboard and VGA output through a dummy console. It proves the feasibility of the card-centric framework and offers a glimpse of the future of smart card technology.

A new multistage preamplifier with offset reduction for use in high-speed comparator is presented. The proposed circuit is based on the cascade of the modified input offset storage amplifiers and the output offset storage amplifier in pipeline arrangement. Not only does the topology maintain a good input common-mode range, it exhibits faster speed due to the reduced capacitive loads. Using AMS 0.35 /spl mu/m CMOS process model, the simulation result has shown that the new preamplifier has achieved a settling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical power consumption.

A class-AB CMOS power amplifier, which embodies new error amplifiers and adopts the embedded frequency compensation in a multistage topology, is presented. The simulated result has shown that the unity gain-bandwidth is 7.3 MHz. The quiescent supply current is 1.43 mA whilst the output stage delivers maximum 40 mA into a 32 /spl Omega/ // 220 pF load. The amplifier exhibits -83 dB THD at a closed-loop gain of 20 dB for 1 kHz, 2 Vpp output at a 3 V supply in a 0.6 /spl mu/m CMOS technology.

A new switched-capacitor interface circuit with differential-input single-ended output (DISO) for integrated sensor applications is presented. The circuit adopts the correlated double sampling technique combined with the auxiliary amplifier structure to cancel the 1/f noise and to minimize the systematic offset and errors due to charge injection. The simulated results show that the circuit exhibits a DC offset of 7 /spl mu/V and consumes 620 /spl mu/A at a single 5 V supply, with a sample rate 128 kHz in 0.8 /spl mu/m CMOS technology.